Sr Layout Engineer - DPG LPDDR

Job Title

Sr Layout Engineer - DPG LPDDR

Role Summary

Responsible for physical layout of analog, mixed-signal, and high-speed LPDDR PHY blocks to achieve silicon-accurate performance, manufacturability, and JEDEC compliance. Works within a layout team supporting LPDDR interface IP and collaborates with circuit, verification, architecture, and silicon debug teams to enable first-silicon success and high-volume production.

Experience Level

Senior level. The role expects approximately 6+ years of hands-on experience in analog/mixed-signal layout and high-speed interfaces.

Responsibilities

The role focuses on physical implementation and closure of LPDDR PHY blocks and related digital/mixed-signal circuitry.

• Own custom analog and mixed-signal layout for critical LPDDR PHY blocks (datapath, bias networks, IO analog frontends, reference circuits) ensuring robustness across PVT, low noise coupling, and high matching accuracy.
• Execute high-speed LPDDR interface layout addressing signal integrity: skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
• Design and optimize array-based layouts for DQ/DQS byte lanes, CA lanes, and replica paths with strict symmetry, pitch matching, repeatability, and scalability.
• Implement custom digital block layouts within the PHY (training logic, calibration engines, test/debug circuitry) with attention to clocking, congestion, and interaction with sensitive analog regions.
• Drive layout-aware co-design with circuit designers, incorporating parasitic awareness early in the design cycle to meet timing, noise, IR, and EM requirements.
• Apply power distribution, grounding, and isolation best practices (guard rings, deep-N-well, decoupling, domain separation) to protect analog and high-speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlate extraction with simulation results for silicon-accurate performance.
• Support post-layout optimization and ECOs to resolve margin, yield, and manufacturability issues while maintaining JEDEC compliance.
• Collaborate with architecture, circuit, verification, and silicon debug teams to enable first-silicon success and HVM readiness.
• Contribute to PPA optimization with focus on low power, area efficiency, and reliability for LPDDR applications.
• Contribute to layout flow improvement and automation efforts; apply data-driven methods where applicable.

Requirements

Must-have technical skills and experience for immediate success in this role.

• 6+ years of hands-on experience in analog/mixed-signal layout and high-speed serial interfaces.
• Demonstrated physical layout experience for high-speed memory interfaces (LPDDR PHY datapath, IO, DQ/DQS, CA lanes).
• Strong signal integrity and power-integrity skills: skew control, impedance matching, shielding, crosstalk mitigation, IR/EM analysis.
• Proven experience with DRC/LVS closure, parasitic extraction, and correlation to simulation.
• Practical knowledge of power distribution, grounding, guard rings, deep-N-well usage, decoupling strategies, and domain isolation.
• Experience handling post-layout ECOs, yield and manufacturability concerns, and JEDEC compliance for LPDDR.
• Ability to collaborate effectively with circuit designers, verification, architecture, and silicon debug teams.

Nice-to-have:

• Experience with layout automation and VXL-compatible layout flows.
• Familiarity with AI/ML-driven layout automation, data-driven optimization, or debug/correlation workflows.
• Prior experience with calibration/training engines and test/debug circuitry for high-speed PHYs.
• Experience with high-volume manufacturing and silicon bring-up.

Education Requirements

B.Tech/B.E. in Electronics, Electronics & Communications, or VLSI Engineering; M.Tech in Electronics Engineering, Microelectronics, or VLSI Engineering (degrees and fields specified in source).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.