Sr Layout Designer - Analog/Mixed Signal

Job Title

Sr Layout Designer - Analog/Mixed Signal

Role Summary

Senior physical layout engineer responsible for delivering high-performance analog and mixed-signal layouts (ADC/DAC, SerDes) in advanced process nodes. The role leads layout implementation, verification, tape-out activities and cross-team coordination with circuit designers, foundry and CAD teams.

Experience Level

Senior — requires 10+ years of industry experience in analog/mixed-signal layout design.

Responsibilities

Primary responsibilities include ownership of layout design, verification, and tape-out coordination for high-speed analog/mixed-signal blocks.

• Own physical layout of ADC/DAC, SerDes, and analog/mixed-signal circuits across advanced nodes (2nm–16nm).
• Plan and implement layouts optimized for signal integrity, matching, symmetry, and parasitic minimization.
• Collaborate with circuit designers to meet power, performance, and area (PPA) targets while ensuring DFM compliance.
• Execute floorplanning, block partitioning, power grid design, guard rings, and substrate isolation strategies.
• Perform LVS, DRC, ERC, parasitic extraction (PEX) and close verification loops for signoff readiness.
• Coordinate tape-out activities: documentation, sign-off checks, and multi-team handoffs.
• Work with foundry and CAD teams to optimize flows for FinFET and GAA technologies.
• Mentor and lead junior layout engineers and help define layout methodologies and automation opportunities.

Requirements

Must-have technical skills, process experience, and behavioral expectations.

• 10+ years of analog/mixed-signal layout experience in advanced nodes (2nm–16nm); TSMC experience preferred.
• Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits with attention to timing, matching, shielding, and electromigration.
• Hands-on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and strong schematic-to-layout (S2L) workflow knowledge.
• Experience with FinFET and/or Gate-All-Around (GAA) process technologies.
• Deep knowledge of analog layout techniques: current mirrors, differential pairs, passive components, biasing, shielding, guard rings, and ESD structures.
• Experience leading tape-outs, including sign-off checks and cross-team coordination.
• Strong analytical, problem-solving, written and oral communication skills; ability to articulate decisions and lead junior engineers.
• Demonstrated job stability and consistent prior employment history (no frequent job hopping).

Nice-to-have:

• Familiarity with Mentor/Siemens Calibre verification tools and scripting (Skill, Python, Tcl) for layout automation.
• Exposure to top-level floorplanning and mixed-signal SoC integration.
• Experience optimizing for signal integrity, IR drop, and thermal effects in high-speed designs.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (required).

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.