Sr. Design for Test (DFT) Engineer

Job Title

Senior Design for Test (DFT) Engineer

Role Summary

The Senior DFT Engineer will design, validate, and deploy test solutions for integrated digital, analog, and photonic ASICs. You will collaborate with RTL, physical-design, and product teams to enable pre-silicon verification, post-silicon bring-up, and volume test strategies for high-performance AI hardware.

Experience Level

Senior — minimum 5 years of industry experience working on DFT-related activities for advanced ASIC designs.

Responsibilities

Primary responsibilities include architecting and delivering scalable DFT solutions across chip, module, and system levels.

• Create chip, module, and system-level DFT solutions for a photonics-based AI platform.
• Develop and deploy DFT methodologies for next-generation products.
• Provide integrated test architecture covering ATPG, boundary-scan, and memory test.
• Integrate DFT with RTL front-end and backend physical design flows.
• Build automated flows and scripts to scale team testing capabilities.
• Support initial silicon bring-up, debug, and validation of test implementations.
• Collaborate with cross-functional teams to meet product and schedule requirements.

Requirements

Core technical skills and experience required; preferred skills listed separately.

• At least 5 years of industry experience on DFT activities for advanced ASIC designs.
• Proven experience in pre-silicon design activities and DFT implementation validation.
• Practical experience with scripting for automation (Python or TCL).
• Solid understanding of DFT concepts: scan, ATPG, memory test, JTAG/boundary-scan.
• Familiarity with SoC architecture and hardware description languages (e.g., Verilog).
• Experience using commercial EDA DFT tools for MBIST, ATPG, and boundary scan.
• Ability to work independently on routine tasks and escalate unfamiliar issues appropriately.
• Ability to support silicon debug, gather and analyze ATE data.
• Capacity to comply with U.S. export control laws.

• Experience across logic design, validation, implementation, pattern generation, and coverage analysis.
• Multiple production-quality ASIC tapeouts and experience with trade-offs between test quality and test time.
• Understanding of timing, physical-design, and power impacts of DFT structures.
• Strong cross-functional communication and teamwork skills.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required. A Master’s degree in Electrical Engineering, Computer Engineering, or related field is preferred.

About the Company

Company: Lightmatter

Headquarters: Boston, Massachusetts, USA

Lightmatter develops photonic AI data-center infrastructure and optical chips for extreme-scale AI and HPC. The company invented the Passage 3D‑stacked photonics engine to provide high-bandwidth, low-latency interconnects across large-scale processors and raised $400M in Series D financing at a reported $4.4B valuation.