Sr Design Engineering Architect
Cadence Design SystemsRole Summary
The Sr Design Engineering Architect will work within the Interface Controller IP development team, focusing on PCIe architecture as well as ARM CPU subsystem architecture, including the design of the memory subsystem, IO, and cache subsystems.
Experience Level
Mid-Level to Senior position with 6-16 years of relevant experience.
Responsibilities
The role includes the following responsibilities:
- Design and support RTL for PCIe/CXL/IDE/UALink IP solutions.
- Add new features to existing RTL and ensure compliance with LINT and CDC design guidelines.
- Support customer configurations as part of verification regressions.
- Collaborate with IP development teams.
Requirements
Required qualifications include:
- BE/BTech/ME/MTech in Electrical/Electronics/VLSI.
- Core RTL Design experience of 6-16 years using Verilog.
- Strong knowledge of System Verilog and UVM-based environments.
- Expertise in CPU subsystem architecture and relevant memory subsystem design.
- Desirable experience in PCIe/CXL/IDE protocols and scripting knowledge.
- Experience in IP development teams is a plus.
Education Requirements
Must have a degree in Electrical, Electronics, or VLSI engineering.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
