Sr. Compiler Engineer

Job Title

Senior Compiler Engineer

Role Summary

Build and own backend compiler components that translate ML workloads into microcode for Tensordyne inference hardware. The role focuses on maximizing hardware utilization for generative AI inference by implementing lowering, scheduling, allocation, and microcode generation for a novel accelerator architecture.

The team spans compiler, runtime, kernel, ISA, and silicon co-design; you will work across those boundaries to improve end-to-end performance and enable both engineer-driven and agent-driven optimization workflows.

Experience Level

Senior. The posting targets an experienced engineer with substantial production compiler work and system-level performance reasoning; no specific years-of-experience requirement was stated.

Responsibilities

Key responsibilities include translating ML workloads to efficient microcode and closing the gap between theoretical and achieved throughput on custom hardware.

• Implement and improve backend compilation stages: lowering, instruction scheduling, register and resource allocation, and microcode generation.
• Optimize for the memory hierarchy: SRAM residency, HBM traffic, DMA orchestration, data layout, rematerialization, and movement to keep compute bound.
• Develop tiling, fusion, and software-pipelining strategies to increase sustained throughput.
• Design compiler interfaces and diagnostics suitable for both human engineers and agents: structured IR access, machine-readable diagnostics, and searchable tuning spaces.
• Address dynamic workloads: handle dynamic shapes, reduce compile latency, manage KV-caches, and balance time-to-first-token versus steady-state throughput.
• Build and continuously calibrate performance cost models against hardware and feed compiler insights back into ISA and microarchitecture requirements.

Requirements

Must-have technical qualifications and desirable skills.

• Production compiler experience in code generation, optimization, or graph mapping with demonstrable shipped results and measurable impact.
• Practical experience with MLIR and/or LLVM and contributions or significant work on an active compiler stack (LLVM, MLIR, TVM, IREE, XLA, Triton, Inductor, or equivalent).
• Strong modern C++ skills and a disciplined approach to testing and correctness; Rust is a plus.
• Experience targeting custom accelerators or non-standard ISAs and ability to read and reason about microarchitecture specifications.
• Strong performance intuition across memory hierarchy, data movement, parallelism, synchronization, and occupancy.
• Co-design mindset: willingness to work across compiler, kernels, runtime, ISA, and silicon boundaries.

Nice-to-have:

• Work on autotuning, auto-scheduling, or polyhedral compilation.
• Hands-on experience using agents in compiler, kernel-generation, or optimization loops.
• CUDA/Triton experience, familiarity with CUTLASS or NCCL ecosystems.
• Experience with VLIW, systolic, dataflow, or other unconventional architectures.
• Public open-source compiler contributions that can be reviewed.

Education Requirements

Not specified.

About the Company

Company: Tensordyne

Tensordyne is a startup developing high-performance, low-power AI inference processors and multi-chip systems for generative AI acceleration in data centers. The company focuses on ASIC design, verification, and integration of computational accelerators with third-party SoC IP.