SPE Signal Integrity (Sr. Principal Engineer - Signal Integrity)

Job Title

SPE Signal Integrity (Sr. Principal Engineer - Signal Integrity)

Role Summary

Senior signal-integrity engineer on the Memory Interface Chips BU SI/PI team. Report to the Senior Director of Engineering and lead modeling, analysis and simulation of signal and power integrity for high-speed DDR interfaces (up to 16000+ MT/s).

Hybrid role expected to average about three days per week onsite; responsible for SI/PI methodology, package and PCB trade studies, lab correlation and customer collaboration.

Experience Level

Senior level - requires 10+ years of industry experience with multi-year exposure to DDR4/DDR5 and high-speed interface simulation.

Responsibilities

Key technical and cross-functional responsibilities.

• Develop SI/PI methodologies and perform channel and package simulations for DDR product portfolio.
• Define system-level specifications and design requirements with design and validation teams (packaging, PCB routing, decoupling, channel/jitter analysis).
• Provide SI-driven design guidelines and recommendations based on simulation and silicon correlation to meet performance targets (e.g., RMT).
• Collaborate with customers to identify optimal SI/PI solutions and trade-offs in system context.
• Support lab debug and bring-up; correlate measurements to simulations using scopes, TDRs, VNAs, etc.
• Work with cross-functional teams to influence IC-PKG-BRD co-design decisions and BGA assignments.

Requirements

Must-have technical skills and experience; listed as required vs. desirable where possible.

• Must-have: Extensive SI/PI and package design experience; proven technical leadership on high-speed memory or SERDES interfaces.
• Must-have: Prior experience simulating DDR4/DDR5 and/or SERDES interfaces; strong theoretical background in EM and transmission-line theory.
• Must-have: Familiarity with equalization techniques (FIR/FFE/DFE/CTLE) and ability to include crosstalk/jitter effects in low-BER simulations.
• Must-have: Proficient with circuit and channel simulators (Spice, ADS) and commercial EDA tools such as ADS, HFSS, Q3D/PowerSI.
• Must-have: Experience editing APD/Allegro layout files, BGA assignment methodology, and evaluating package/PCB trade-offs.
• Must-have: Experience correlating simulation with lab measurements (real-time/sampling scopes, VNA, TDR).
• Required soft skills: Strong written and verbal communication; ability to engage with customers and cross-functional teams.
• Nice-to-have: Experience with RedHawk/Totem, XcitePI, Virtuoso, lab characterization of passive components, and knowledge of server-system architecture (CPUs to DRAM on DIMMs).
• Nice-to-have: Basic circuit design knowledge for high-speed links.

Education Requirements

MS or PhD in Electrical Engineering is specified; the posting also requires 10+ years of industry experience and exposure to DDR4/DDR5. Equivalent practical experience is not explicitly stated.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.