SPE Logic Design Engineer
RambusJob Title
SPE Logic Design Engineer
Role Summary
Design synthesizable IP for leading-edge PCIe and CXL standards as part of the IP Engineering Logic Design team. Responsible for micro-architecture, RTL development, FPGA prototyping, and silicon-validation quality checks.
Work with a distributed international team in a hybrid environment (expected ~3 days onsite per week).
Experience Level
Senior — 7+ years of relevant experience.
Responsibilities
The engineer will contribute to design, verification, prototyping, and quality assurance of PCIe/CXL IP.
- Follow developments in PCIe and CXL standards and apply them to IP design.
- Micro-architecture and RTL design of advanced PCIe/CXL IP (PCIe7 and beyond).
- Participate in FPGA prototyping and hardware validation.
- Run and improve ASIC/FPGA quality checks: synthesis, CDC/RDC, linting, simulation.
- Collaborate with global engineering teams.
- Drive technical improvements across the IP design domain.
Requirements
Must-have technical skills and experience; desirable skills listed separately.
- 7+ years of relevant experience in logic/IP design.
- Proficient in Verilog and SystemVerilog.
- Strong communication skills in English and ability to work with international teams.
Nice-to-have:
- Knowledge of UPF (power intent).
- Experience with ASIC/FPGA design flows and tools (synthesis, CDC/RDC/linting, Quartus, Vivado).
Education Requirements
Not specified.
About the Company
Company: Rambus
Headquarters: Sunnyvale, California, USA
Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.
