Solutions Engineer - AE

Job Title

Solutions Engineer - AE

Role Summary

Provide technical leadership to customers deploying and optimizing advanced packaging, 2.5D/3D‑IC, chiplet, AI/HPC and heterogeneous integration solutions using Cadence tool flows. The role combines customer-facing application support, solution workflow development, and collaboration with sales and R&D to drive product adoption and customer success.

Experience Level

Senior level - this role requires extensive domain experience (see Education Requirements for degree guidance).

Responsibilities

Key responsibilities focus on customer engagement, technical enablement, and methodology development for advanced packaging and 3D‑IC design.

• Provide technical leadership and application support for advanced packaging and 3D‑IC design solutions.
• Assist customers with architecture, implementation, and methodology for package and chiplet-based designs.
• Develop, demonstrate, and document end-to-end packaging workflows (organic substrates, silicon interposers, WLP, 2.5D/3D‑IC, chiplet architectures).
• Support customer evaluations, proofs-of-concept, benchmarks, and production deployments.
• Deliver technical presentations, product demonstrations, workshops, and training.
• Collaborate with sales for technical pre-sales and with R&D to convey customer requirements and enhancement requests.
• Support design-signoff activities: DRC/LVS, connectivity verification, electrical rule checking, thermal analysis, signal integrity (SI), and power integrity (PI).
• Create best practices, application notes, reference flows, and customer success methodologies.

Requirements

Essential skills and experience for the role; degree details are listed under Education Requirements.

• 10+ years experience in semiconductor packaging, IC packaging, PCB, substrate, or interposer design.
• Strong knowledge of advanced package design methodologies, 2.5D/3D‑IC integration, and chiplet-based architectures.
• Experience with package layout, routing, constraint management, and signoff; understanding of stackups, bump planning, escape routing, and substrate technologies.
• Knowledge of package manufacturing and assembly processes, high-speed signal design, and power delivery networks.
• Practical experience with SI/PI and thermal analysis; familiarity with electrical rule checking and connectivity verification.
• Excellent customer-facing communication and presentation skills; ability to work independently and with global teams.
• Willingness to travel approximately 2–5% for customer engagements.

Nice-to-have:

• Experience with Cadence Integrity 3D‑IC Platform, Cadence Sigrity, Clarity 3D Solver, or Cadence Allegro X APD.
• Knowledge of UCIe, HBM, AI accelerator packaging, heterogeneous integration, and foundry/OSAT design flows.
• Experience supporting production deployments and reliability/assembly considerations.

Education Requirements

Bachelor's degree required; Master's preferred, in Electrical or Electronics Engineering or a related discipline. The role also specifies 10+ years of relevant semiconductor/IC packaging experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.