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Solutions DFT Engineer (Staff)

Synopsys
September 30, 2026
Full-time
On-site
Bengaluru, Karnataka, India
DFT Jobs, Level - Senior

Job Title

Solutions DFT Engineer (Staff)

Role Summary

Staff-level DFT engineer responsible for delivering end-to-end design-for-test (DFT) solutions for complex digital SoCs. The role combines technical implementation, silicon diagnostics, and direct customer engagement to ensure first-time silicon success.

The position works with customers across automotive, AI, and consumer electronics to plan scan/MBIST architectures, validate test solutions, and transfer methodologies into production flows.

Experience Level

Senior / Staff level. The posting requires substantial experience (see Education Requirements for degree-and-years guidance).

Responsibilities

Deliver technical DFT work and customer-facing support across the product lifecycle.

  • Design and deliver DFT architecture and implementation: scan insertion, test access networks, MBIST, and IEEE 1687 integration.
  • Generate and validate ATPG patterns and support silicon bring-up and diagnostics analysis.
  • Participate in customer design reviews to identify test gaps and recommend concrete improvements to increase coverage or reduce test time.
  • Prototype and validate new DFT methodologies with Solution Architects before customer deployment.
  • Provide technical support, training, workshops, and hands-on problem resolution for customer teams.
  • Perform product demonstrations, competitive benchmarking, and evaluations to support sales and adoption.
  • Analyze silicon test data, diagnose failures, and present findings and remediation plans to stakeholders.

Requirements

Key technical skills and experience required for day-one impact. Degree requirements are summarized separately under Education Requirements.

  • Hands-on experience with RTL coding, DFT insertion processes, ATPG pattern generation, and silicon bring-up for digital ICs.
  • Deep understanding of scan architectures, fault models, test access networks, and IEEE standards (1149.1, 1500, 1687).
  • Proven ability to implement and validate scan for large multi-IP SoCs with complex hierarchies and multiple clock domains.
  • Familiarity with industry DFT tools and flows; exposure to Synopsys TetraMAX, DFT Compiler, or MBIST Architect is valuable.
  • Strong written and verbal communication skills for both technical and non-technical audiences.

Nice-to-have:

  • Experience with MBIST architecture planning and integration, especially in automotive or safety-critical environments.
  • Prior work creating or scaling DFT methodologies across multiple accounts.

Education Requirements

Bachelor's degree with 7+ years' relevant experience, or Master's degree with 5+ years' relevant experience in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-09-28