Software Engineer — Package Layout Design (3D‑IC Solutions)

Job Title

Software Engineer — Package Layout Design (3D‑IC Solutions)

Role Summary

Develop and integrate software and workflows for advanced 2.5D/3D system‑in‑package (SiP) designs. The role focuses on linking physical implementation, package/layout tools, and 3D‑IC planning to support architectural planning, multi‑die analysis (electrical, thermal, mechanical), verification, and manufacturing test.

Position sits within R&D for Siemens EDA and works on product development and tool interoperability for advanced packaging solutions.

Experience Level

Senior — typically requires 5+ years of relevant industry experience.

Responsibilities

Primary responsibilities include tool integration, methodology development, assembly and verification of 3D packages, automation, and technical guidance.

• Integrate physical design and 3D‑IC planning tools for multi‑die advanced packaging workflows.
• Develop methodologies for constructing and integrating chiplet designs within physical implementation and 3D‑IC planning environments.
• Create and integrate substrate/package layouts and ensure correct data transfer and assembly in planning tools.
• Perform 3D assembly of chiplets and packages and execute verification including LVS and DRC.
• Develop scripts and automation (Python, Tcl/Tk, Bash, or similar) to streamline workflows and improve tool interoperability.
• Diagnose and resolve technical issues related to tool integration, packaging methodologies, and verification.
• Provide technical guidance, demonstrations, and documentation to internal teams and stakeholders.
• Track advances in 3D‑IC and packaging technologies and evaluate AI applications to optimize flows.

Requirements

Must-have technical skills and professional abilities; preferred items listed separately.

• Hands‑on experience with advanced packaging design and 3D package construction.
• Proficiency in scripting and automation (Python, Tcl/Tk, Bash, or similar).
• Strong understanding of advanced packaging design principles and methodologies.
• Experience with physical implementation/place & route tools and 3D‑IC planning/integration tools.
• Working knowledge of package/substrate layout design tools.
• Familiarity with 3D verification tools and LVS/DRC processes in 3D‑IC contexts.
• Strong problem‑solving skills and ability to work independently and collaboratively in a fast‑paced environment.
• Effective written and verbal communication skills for technical audiences.

Preferred / nice‑to‑have:

• Experience with Cadence APD/SiP, Siemens Xpedition, Siemens Innovator 3D IC, Cadence Integrity/Innovus, or Synopsys 3DIC Compiler.
• Familiarity with applying AI/ML techniques to EDA workflows.
• Knowledge of advanced process nodes and their implications for packaging.
• Experience with IC analysis tools (HyperLynx, HFSS, Redhawk, Voltus, PrimeTime) and multi‑physics analysis (SI/PI, DC drop, thermal, thermo‑mechanical stress).
• Experience with version control (Perforce, Git), PLM/IPLM systems, and agile development processes.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a closely related technical field required, plus 5+ years of relevant industry experience.

About the Company

Company: Siemens

Headquarters: Munich, Germany

Siemens EDA is a leading global provider of Electronic Design Automation (EDA) products and systems. Their innovative solutions enable companies to enhance the development of electronic products efficiently and effectively, keeping pace with the complex demands of technology and physics. Siemens is committed to delivering advanced workflow solutions that integrate both EDA and MCAD tools for multi-domain design and manufacturing in the semiconductor industry.