Software Engineer II - Verification using SV/UVM
Cadence Design SystemsRole Summary
The Software Engineer II will develop verification environments and implement test features for Verification IP tools. This role involves working with a skilled team to create innovative solutions in the field of electronic design.
Experience Level
Mid-level, with 2 to 4 years of relevant experience required.
Responsibilities
The key responsibilities include:
- Design, development, and verification of Verification IP (VIP).
Requirements
Must have the following qualifications and skills:
- Proficiency in functional verification using SV/UVM.
- Strong debugging skills.
- Solid understanding of Digital Electronics and Programming fundamentals.
- Hands-on experience with C/C++ and scripting.
- Desirable experience with MIPI UFS stack.
- Strong analytical and communication skills.
Education Requirements
BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
