SoC Verification Staff Engineer

Job Title

SoC Verification Staff Engineer

Role Summary

Staff verification engineer responsible for block and subsystem verification of high-speed interface IP used in SoCs. You will design and implement UVM/SystemVerilog testbenches, create verification plans, run regressions, debug RTL/testbench issues, and drive verification to signoff.

This role sits on the Subsystem Verification Team in Ho Chi Minh City and collaborates with RTL designers and global verification teams to deliver silicon-proven IP for AI, 5G, HPC, and automotive systems.

Experience Level

Senior — typically 6+ years of hands-on design verification experience in semiconductor design/verification.

Responsibilities

Primary responsibilities include defining verification scope, building test environments, and closing coverage to signoff.

• Define block and subsystem verification plans mapped to specs and protocols.
• Build UVM testbenches in SystemVerilog: agents, scoreboards, coverage models, and assertion monitors.
• Create constrained-random and directed tests for protocol compliance, corner cases, and error injection.
• Debug RTL and testbench failures using simulators and waveform analysis to find root cause.
• Collaborate with RTL designers and global verification engineers on design intent and coverage goals.
• Apply formal verification techniques to prove properties and close coverage gaps.
• Track coverage metrics and drive verification closure through iterative test plans.

Requirements

Technical must-haves first, followed by valuable additions.

Must-have

• 6+ years of hands-on design verification experience in the semiconductor industry.
• Strong proficiency in SystemVerilog and UVM for building testbenches and implementing coverage.
• Working knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR.
• Experience with industry simulators (VCS, Xcelium, or Questa) and version control systems.
• Scripting skills for automation and regression management (Python, Perl, or Tcl).
• Proven debugging skills with waveform analysis across clock domains.
• Ability to work and communicate with distributed RTL and verification teams.

Nice-to-have

• Experience applying formal verification techniques to close coverage gaps.
• Prior experience verifying interface IP for AI, networking, or automotive applications.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.