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SoC Verification Senior Engineer

Synopsys
August 22, 2026
Full-time
On-site
Ho Chi Minh City, Vietnam
Verification Jobs, Level - Senior

Job Title

SoC Verification Senior Engineer

Role Summary

Senior verification engineer responsible for defining and executing block and subsystem verification for high-speed interface IP. Work on UVM/SystemVerilog testbenches, debug RTL and testbench failures, and collaborate with RTL designers and global verification teams.

Join a newly formed Subsystem Verification Team in Ho Chi Minh City focused on silicon-proven interface IP used in AI, 5G, HPC, and automotive systems.

Experience Level

Senior. The posting indicates approximately 2+ years of hands-on design verification experience; the title denotes a senior role.

Responsibilities

Primary verification responsibilities include:

  • Define block and subsystem verification plans that map to specifications and protocol requirements.
  • Design and implement UVM testbenches in SystemVerilog, including agents, scoreboards, coverage models, and assertion monitors.
  • Write constrained-random and directed tests to exercise protocol compliance, corner cases, and error injection scenarios.
  • Debug RTL and testbench failures using simulators and waveform analysis to root-cause and resolve issues.
  • Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals.
  • Apply formal verification techniques where appropriate to prove properties and close coverage gaps.
  • Track coverage metrics and drive verification closure until signoff.

Requirements

Must-have technical skills and experience:

  • 2+ years of hands-on design verification experience in the semiconductor industry.
  • Strong proficiency in SystemVerilog and UVM for building testbenches and implementing coverage.
  • Working knowledge of at least one protocol such as AMBA, PCIe, CXL, UCIe, Ethernet, HBM, or DDR.
  • Experience with simulators like VCS, Xcelium, or Questa and with version control systems.
  • Scripting skills for automation and regression management (Python, Perl, or Tcl).
  • Ability to debug complex issues across clock domains using waveform analysis and simulation logs.
  • Good communication skills for collaboration with distributed RTL and verification teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-08-20