SoC Top-Level Physical Design Engineer, Annapurna Labs

Job Title

SoC Top-Level Physical Design Engineer, Annapurna Labs

Role Summary

Design and verify full-chip physical implementation and integration of custom SoCs used in cloud-scale machine learning servers. The role is part of the Cloud-Scale Machine Learning Acceleration team and focuses on floorplanning, placement, physical verification, and tape-out for advanced technology nodes.

Experience Level

Senior. Role expects significant hands-on experience in physical verification and chip-level integration for advanced nodes; see Requirements for specific years-of-experience guidance.

Responsibilities

Primary responsibilities include driving chip-level physical implementation, verification, and integration across design and foundry interactions.

• Drive full-chip floorplan, placement, integration, physical verification (PV) signoff, and tape-out.
• Collaborate with front-end teams to incorporate RTL constraints and drive physical considerations early in the design cycle.
• Define, execute, and optimize physical verification and integration methodologies using industry-standard EDA tools (e.g., Calibre, IC Validator, Foundry tools).
• Perform DRC, LVS, and PERC verification; debug and resolve PV issues with layout and design teams.
• Interface with foundries for rule deck updates, MT form interactions, and waiver handling.
• Develop and maintain verification runsets and methodologies; analyze QOR and design-parameter trends.
• Mentor and provide technical guidance to junior engineers during integration and closure.

Requirements

Must-have technical skills and experience.

Must-have:

• Experience scripting with Python, Perl, Bash, or PowerShell.
• 5+ years of hands-on experience in physical verification for advanced technology nodes.
• Understanding of backend physical design flows for chip-top and subsystems (e.g., Foundry/Innovus flows).
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules.
• Proven track record of successful tape-outs.
• Strong communication and collaboration skills.

Nice-to-have:

• Experience mentoring, leading, or managing junior engineers.
• Integration and verification experience at advanced nodes (5 nm or below).
• Familiarity with custom and digital design flows; DFM methodologies.
• Expertise in reliability verification (ESD, EM, IR drop).
• Experience addressing physical design challenges across DDR, PCIe, and fabric interfaces.
• Experience extracting design parameters and analyzing QOR metrics and trends.

Education Requirements

Bachelor of Science with ~10+ years relevant experience, or Master of Science with ~7+ years in Electrical Engineering, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: Amazon

Headquarters: Seattle, Washington, United States

Amazon is a global leader in e-commerce and cloud computing, committed to delivering fast, reliable services across diverse sectors. The company's innovative technologies include AWS, Kindle, and Echo, as well as developing low Earth orbit satellite networks for improved internet connectivity worldwide.