SoC Timing (Static Timing Analysis/STA) Engineer, HBM

Job Title

SoC Timing (Static Timing Analysis/STA) Engineer, HBM

Role Summary

Join Micron's Heterogeneous Integration Group (HIG) to own chip-level static timing analysis (STA) and timing sign-off for next-generation HBM-enabled die. The role focuses on constraint development, timing closure, methodology, and pre-/post-silicon timing correlation across RTL, physical design, verification, and product teams.

Experience Level

Senior — hands-on technical role. The posting specifies 10+ years of relevant chip-level STA and sign-off experience, including multiple tape-outs at 5nm or below.

Responsibilities

Primary responsibilities include timing ownership, constraint management, automation, and collaboration to achieve sign-off-ready timing results.

• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, voltages, and temperatures.
• Develop, validate, and maintain sign-off-quality Synopsys Design Constraints (SDC) for clocks, resets, HBM interfaces, DFT, and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels via critical path analysis, ECOs, and coordination with physical design on placement, CTS, and routing.
• Perform multi-mode, multi-corner (MMMC) analysis, including CDC timing, on-chip variation (OCV/AOCV/POCV), and power-aware timing methodologies.
• Lead signal integrity and crosstalk analysis; identify noise-induced timing issues and work with physical design on mitigations.
• Build and maintain STA automation and flows using Python and Tcl for reporting, regression tracking, dashboards, and sign-off readiness.
• Conduct post-silicon timing correlation and define organization-wide STA methods, sign-off standards, readiness reviews, and tape-out gates.
• Mentor junior engineers and collaborate with Physical Build, RTL Build, Verification, Build-for-Test, Product Engineering, and Test teams to meet timing requirements throughout the build cycle.

Requirements

Must-have technical skills and practical experience followed by preferred (nice-to-have) skills.

• Must-have: 10+ years owning chip-level STA and full timing sign-off on multiple tape-outs at 5nm or below.
• Must-have: Deep expertise with Synopsys PrimeTime and/or Cadence Tempus.
• Must-have: Expert understanding of MMMC analysis, on-chip variation, signal integrity, and power-aware timing.
• Must-have: Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Must-have: Proficiency in Python and/or Tcl for timing-flow automation, constraint management, and quality-of-results reporting.
• Nice-to-have: Experience with HBM, DRAM, or memory-centric SoC designs.
• Nice-to-have: Exposure to design-for-test timing (scan, MBIST, JTAG).
• Nice-to-have: Experience with chiplet-based or 3D IC designs and die-to-die interface timing methodologies.
• Nice-to-have: Familiarity with foundry PDKs, Liberty timing models, and advanced noise/variation modeling.
• Nice-to-have: Good communication skills and willingness to learn/apply Agentic AI to improve workflows.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.