SoC Timing (Static Timing Analysis/STA) Engineer, HBM

Job Title

SoC Timing (Static Timing Analysis/STA) Engineer, HBM

Role Summary

Senior static timing analysis (STA) engineer in the Heterogeneous Integration Group responsible for chip-level timing sign-off for HBM die. The role owns timing closure and methodology from early design through tape-out, working closely with RTL, physical design, architecture, DFT, verification, product, and test teams.

Experience Level

Senior — requires substantial hands-on experience; posting specifies 10+ years of relevant STA and sign-off experience.

Responsibilities

Primary responsibilities include ownership of chip-level STA, constraint development, timing closure, methodology, and mentoring.

• Own end-to-end chip-level static timing analysis and sign-off across checks, modes, corners, voltage and temperature conditions.
• Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, HBM interfaces, DFT, and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels via critical-path analysis, ECOs, and close collaboration with physical design on placement, CTS, and routing.
• Perform multi-mode multi-corner (MMMC) analysis including clock-domain crossing timing and on-chip variation methodologies (OCV, AOCV, POCV).
• Lead signal integrity and crosstalk analysis; identify noise-induced timing issues and coordinate mitigation with physical design teams.
• Build and maintain STA automation and flows using Python and Tcl for reporting, regression tracking, dashboards, and sign-off readiness.
• Conduct post-silicon timing correlation; define and drive timing methodology, sign-off standards, readiness reviews, and tape-out sign-off gates; communicate status and risks to design leads and management.
• Mentor junior engineers and contribute to timing documentation and cross-functional collaboration throughout the design cycle.

Requirements

Key required skills and experience followed by preferred qualifications.

Must-have:

• 10+ years of hands-on experience owning chip-level STA and full timing sign-off on multiple tape-outs at 5nm or below.
• Deep expertise with industry-standard STA tools (e.g., Synopsys PrimeTime and/or Cadence Tempus).
• Expert understanding of advanced timing concepts: MMMC analysis, on-chip variation, signal integrity, and power-aware timing.
• Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Proficiency in Python and/or Tcl scripting for timing flow automation and reporting.

Nice-to-have:

• Experience with high-bandwidth memory (HBM), DRAM, or memory-centric SoC designs.
• Exposure to design-for-test timing (scan, MBIST, JTAG).
• Experience with chiplet or 3D integrated designs and die-to-die interface timing.
• Familiarity with foundry PDKs, Liberty timing models, and advanced noise/variation modeling.
• Strong communication skills for presenting timing status, risks, and readiness to cross-functional teams and leadership.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.