SOC Timing Analysis (STA) Engineer, HBM

Job Title

SOC Timing Analysis (STA) Engineer, HBM

Role Summary

Member of the Heterogeneous Integration Group (HIG) responsible for chip-level static timing sign-off of next-generation HBM die. The role focuses on timing closure, sign-off ownership, methodology development, and pre- and post-silicon timing correlation, working closely with RTL, physical design, architecture, DFT, verification, and product teams.

Experience Level

Senior — requires extensive industry experience in chip-level static timing analysis and demonstrated full timing sign-off ownership on multiple tape-outs (10+ years preferred).

Responsibilities

Primary responsibilities cover end-to-end STA sign-off, timing closure, methodology, automation, and correlation.

• Own end-to-end chip-level static timing analysis and sign-off for all timing checks (setup, hold, recovery, removal, data-to-data) across corners, operating modes, voltages, and temperatures.
• Develop, maintain, and validate Synopsys Design Constraints (SDC) for clock domains, reset trees, HBM interfaces, JTAG, MBIST, DFT, and configuration logic, ensuring sign-off quality and reuse.
• Drive timing closure at block, subsystem, and full-chip levels via critical path analysis, ECOs, and collaboration with placement, CTS, and routing teams.
• Perform multi-mode, multi-corner (MMMC) timing analysis including CDC timing and appropriate on-chip variation derates (OCV/AOCV/POCV).
• Lead signal integrity and crosstalk analysis, identify noise-induced violations, and implement mitigation strategies with physical design teams.
• Conduct DFT timing analysis (scan chain timing, ATPG mode constraints, MBIST timing) and manage timing waivers, regression tracking, and sign-off readiness reporting.
• Develop and maintain automation and flows (Python, Tcl) for constraint generation, report extraction, dashboards, and sign-off processes.
• Perform post-silicon timing correlation, analyze silicon measurements versus pre-silicon predictions, and update timing models and methodologies accordingly.
• Define and drive organization-wide STA methodology, lead readiness reviews and tape-out sign-off gates, and mentor junior engineers.

Requirements

Must-have skills and experience for the role, with preferred items noted separately.

• Must-have: 10+ years of industry experience in chip-level static timing analysis with proven full timing sign-off ownership on multiple tape-outs at advanced process nodes.
• Must-have: Hands-on expertise with Synopsys PrimeTime and/or Cadence Tempus, including configuration of analysis modes, corner libraries, and sign-off decks.
• Must-have: Expert knowledge of multi-mode multi-corner analysis, on-chip variation techniques, signal integrity/crosstalk analysis, and power-aware timing for advanced nodes.
• Must-have: Ability to develop complex SDC constraints for large hierarchical SoC designs and to drive timing closure through collaboration with physical design teams.
• Must-have: Experience across the RTL-to-GDS implementation flow (synthesis, placement, CTS, routing, physical sign-off) and hierarchical STA methodologies.
• Must-have: Experience with post-silicon timing correlation and working with EDA tool vendors to resolve tool issues and improve methodology.
• Nice-to-have: Exposure to DFT concepts (scan, MBIST, ATPG), familiarity with foundry PDKs, Liberty timing models, ECSM/CCS noise models, advanced process variation modeling, and strong scripting (Python/Tcl).
• Nice-to-have: Mentoring experience and strong communication skills for presenting timing status and risks to cross-functional teams.

Education Requirements

Preferred: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. (The posting lists these degrees as preferred; no explicit equivalent-experience statement was provided.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.