SoC RTL Design Engineer for High-Performance SSDs

Job Title

SoC RTL Design Engineer for High-Performance SSDs

Role Summary

Work on SoC RTL for high-performance SSD and AI storage products. Contribute across the RTL design cycle from micro-architecture and coding to timing closure and tapeout readiness.

Collaborate with Design Verification, Silicon Validation, and Firmware teams to deliver production-quality RTL that meets protocol and performance requirements.

Experience Level

Mid-level. Specific years of experience not stated.

Responsibilities

Primary responsibilities include RTL design and delivery for storage SoCs.

• Define micro-architecture and implement RTL in Verilog/SystemVerilog.
• Perform timing closure activities and prepare designs for tapeout.
• Integrate and verify AMBA/PCIe/NAND/DDR protocol interfaces.
• Work with Design Verification, Silicon Validation, and Firmware to resolve issues and enable bring-up.
• Automate tasks and support design flow with scripting (Python).

Requirements

Core technical must-haves and useful additions.

• Practical experience writing and maintaining RTL in Verilog/SystemVerilog.
• Experience with SoC-level RTL design, timing closure, and tapeout readiness.
• Familiarity with on-chip and interconnect protocols: AMBA, PCIe, NAND, DDR.
• Ability to collaborate effectively with verification, validation, and firmware teams.
• Proficiency in scripting for automation and design tasks (Python).
• (Nice to have) Prior experience with SSD or AI storage system designs.

Education Requirements

Not specified.

About the Company

Company: SK hynix America

U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.