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SoC Power Design Engineer (Staff Engineer)

Qualcomm
September 25, 2026
Full-time
On-site
San Diego, California, United States
$145,600 - $218,400 USD yearly
ASIC Design Jobs, Level - Senior

Job Title

SoC Power Design Engineer (Staff Engineer)

Role Summary

Work within Qualcomm's SoC and ASIC design organization on power-focused SoC design and implementation. The role contributes to architecture, RTL design, timing analysis, implementation, and silicon bring-up across mobile, automotive, data center, and AI products.

Primary mission: deliver power-efficient, high-performance SoC power design solutions that meet performance, power, area, timing, and quality targets.

Experience Level

Senior. See Education Requirements for degree and years-of-experience guidance.

Responsibilities

Typical responsibilities include:

  • Participate in architecture, power-aware RTL design, implementation, integration, and optimization of SoC and IP solutions.
  • Develop and validate designs to meet performance, power, area, timing, and quality objectives.
  • Perform RTL design, static timing analysis, timing closure, synthesis, and verification activities.
  • Collaborate with architecture, physical design, verification, methodology, and software teams to deliver complex SoC solutions.
  • Analyze and resolve design and verification issues using sound ASIC engineering practices.
  • Contribute to design reviews and provide technical expertise to drive project execution and quality.
  • Develop and enhance design flows, methodologies, automation frameworks, and engineering tools.
  • Support silicon bring-up and apply silicon learnings to improve future designs and processes.
  • Communicate technical concepts effectively and work across teams.

Requirements

Must-have technical skills and experience:

  • Hands-on ASIC, FPGA, or SoC design and development experience.
  • Strong knowledge of digital design fundamentals and computer architecture.
  • Experience with industry-standard ASIC design, implementation, verification, and timing-analysis tools.
  • Experience with RTL design, synthesis, static timing analysis, and timing closure.
  • Programming or scripting experience (Python, Tcl, Perl, or similar).
  • Strong analytical, problem-solving, communication, and teamwork skills.

Nice-to-have:

  • Experience with low-power design, multi-voltage domains, or power management techniques.
  • Experience with high-performance computing, AI/ML accelerators, data-center designs, or arithmetic/computational IP.
  • Experience developing automation, tools, or design methodologies to improve productivity and quality.

Education Requirements

Required: Bachelor's degree in Science, Engineering, or a related field (commonly Electrical Engineering, Computer Engineering, or Computer Science) with 4+ years of ASIC design/verification/validation/integration experience; OR Master's degree in a related field with 3+ years; OR PhD in a related field with 2+ years. A Master’s is listed as preferred for some candidates.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-24