SoC Power Architecture Engineer

Job Title

SoC Power Architecture Engineer

Role Summary

Design and validate power architecture for mobile SoC ASICs, focusing on chip- and macro-level power domains, power optimization logic, and interactions with PMICs and firmware. Work within a hardware engineering team and collaborate with cross-functional groups (PMIC, software, verification, PCB) to meet power, performance, and thermal targets.

Experience Level

Mid-level; typically 3–5 years of relevant SoC power, low-power design, or hardware engineering experience.

Responsibilities

Primary technical responsibilities the role will own:

• Define chip- and macro-level power domains and power domain crossings.
• Create system-level power models and perform mixed-signal power analysis.
• Design and apply power islanding, power gating, and power isolation strategies.
• Specify structural low-power elements (level shifters, isolation cells) and associated design rules.
• Architect and develop digital power-optimization logic, circuits, and firmware interfaces.
• Coordinate power grid planning with PMIC and PCB teams.
• Produce detailed architecture and implementation documentation for power subsystems.

Requirements

Must-have technical skills and experience. Degrees are summarized in Education Requirements below.

• Practical experience with SoC boot-up behavior, power-domain crossings, and cross-corner timing.
• Familiarity with low-power intent concepts and languages (UPF or CPF).
• Experience with power dissipation sources and power-saving techniques (dynamic clock/voltage scaling).
• Power analysis skills (leakage and dynamic) and understanding of thermal impacts.
• Knowledge of ASIC power grids and PCB power distribution networks.
• Strong written and verbal communication skills for cross-team coordination.

Nice-to-have / preferred:

• Experience with power estimation/reduction tools (PowerArtist, PTPX, Calypto) or structural low-power verification tools (CLP, MVRC).
• Understanding of mobile baseband application processor architectures and power grids.
• UPF-based synthesis and implementation experience (Design Compiler).
• Familiarity with power-management software features and PMIC/voltage-regulator technologies (Buck, LDO).
• Experience leading or mentoring small engineering teams.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical/Electronics Engineering, or a related engineering field is expected. A Master's degree in those fields is preferred; a PhD is also acceptable. The posting indicates typical experience guidance of ~3–5 years; some minimum-qualification variants accept Bachelor's +2+ years or Master's +1+ year of relevant experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.