SoC Physical Verification Engineer, HBM

Job Title

SoC Physical Verification Engineer, HBM

Role Summary

As a Physical Verification Engineer in the Heterogeneous Integration Group (HIG), you will define, execute, and drive sign-off physical verification flows for HBM logic die and memory-centric SoCs. You will collaborate with physical design, EDA tool teams, foundry interfaces, and product engineering to deliver tape-out-ready silicon under schedule, quality, and reliability constraints.

Primary focus: full-chip physical verification (DRC, LVS, ERC, PERC, antenna, DFM) and reliability verification across power domains.

Experience Level

Mid-level; preferred 2+ years of relevant industry experience (per preferred qualifications). The minimum qualifications do not state a strict years requirement.

Responsibilities

Key responsibilities include ownership of sign-off flows and cross-functional verification coordination.

• Lead end-to-end sign-off for full-chip and hierarchical designs: DRC, LVS, ERC, PERC, antenna, and DFM.
• Execute and debug foundry-qualified rule decks, manage waivers, and drive closure to foundry requirements.
• Perform reliability verification across multiple power domains: ESD, latch-up, electromigration, floating nets, and connectivity checks.
• Run density, metal-fill, and CMP checks to ensure yield-aware manufacturability at advanced nodes (3 nm and below).
• Perform parasitic RC extraction and support correlation with post-silicon measurements.
• Develop, maintain, and optimize PV flows, automation, and regression infrastructure using Python, Tcl, Perl, or similar scripting.
• Drive adoption of ML/AI-based verification and PPA optimization tools and leverage AI-assisted workflows.
• Partner with physical design, custom layout, CAD, RTL, product engineering, EDA, and foundry teams (including TSMC) from kick-off through tape-out readiness and sign-off decision gates.

Requirements

Minimum technical skills and experience required; preferred items are listed separately.

• Experience with full-chip or block-level physical verification for advanced-node SoC, memory, or heterogeneous-integration designs.
• Knowledge of physical verification methodologies: DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
• Experience with industry PV tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule-deck development or customization.
• Working knowledge of RTL-to-GDS implementation flows, including place-and-route and extraction and their impact on PV outcomes.
• Strong cross-functional communication to drive verification closure in a global engineering environment.
• Proficiency leveraging AI and AI-enabled development workflows.

Nice-to-have:

• Experience with high-bandwidth memory (HBM), DRAM, multi-die, chiplet, or 2.5D/3D integration PV.
• Background in GPU, CPU, or high-performance accelerator physical implementation at advanced nodes.
• Familiarity with foundry design rule documents, FEOL/BEOL rules, and advanced DFM practices.
• Exposure to post-silicon failure analysis, yield learning, or layout-based debug correlated to silicon behavior.

Education Requirements

Preferred: Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. The posting explicitly allows equivalent practical experience in lieu of an advanced degree.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.