SoC Physical Verification Engineer, HBM

Job Title

SoC Physical Verification Engineer, HBM

Role Summary

Lead physical verification sign-off for advanced-node HBM logic die and memory-centric SoCs within the Heterogeneous Integration Group. Drive DRC/LVS/ERC/PERC/DFM sign-off, tool and rule‑deck development, foundry interfacing, and cross-team coordination from implementation through tape-out readiness.

Experience Level

Mid-level. Micron prefers candidates with relevant industry experience; 2+ years is noted as preferred in the posting.

Responsibilities

Deliver and maintain full-chip and hierarchical physical verification flows and ensure tape-out readiness.

• Implement and execute DRC, LVS, ERC, PERC, antenna checks, and DFM sign-off for full-chip and block-level designs.
• Develop, debug, and maintain foundry‑qualified rule decks; manage waiver processes and close verification issues.
• Perform reliability verification across power domains (ESD, latch-up, electromigration, floating nets) and connectivity checks.
• Run density, metal-fill, and CMP checks for manufacturability at advanced nodes (3nm and below).
• Perform parasitic RC extraction and correlate verification results with post‑silicon measurements.
• Develop and automate verification flows, regressions, and infrastructure using scripting (Python, Tcl, Perl, etc.).
• Drive adoption and evaluation of ML/AI techniques for physical verification and PPA optimization.
• Collaborate with physical design, custom layout, CAD, RTL, product engineering, EDA, and foundry teams (including TSMC) through sign‑off decision gates.

Requirements

Core technical skills and practical experience required to perform the responsibilities below.

Must-have

• Experience with full-chip or block-level physical verification for advanced-node SoC, memory, or heterogeneous‑integration designs.
• Practical experience with physical verification methodologies: DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign‑off.
• Proficiency with industry verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule-deck development or customization.
• Working knowledge of RTL-to-GDS implementation flows (place-and-route, extraction) and how they affect verification outcomes.
• Experience developing and automating flows using scripting languages (Python, Tcl, Perl, or similar).
• Ability to communicate effectively and drive verification closure in a global, multi-disciplinary engineering environment.
• Experience demonstrating or applying AI/AI-enabled development workflows in verification contexts.

Nice-to-have

• Experience with high-bandwidth memory (HBM), DRAM, chiplet/multi-die or 2.5D/3D integration.
• Background in GPU, CPU, or high-performance accelerator physical implementation at advanced nodes.
• Familiarity with foundry rule documents, FEOL/BEOL rules, and advanced DFM guidelines.
• Exposure to post‑silicon failure analysis, yield learning, or layout‑based debug correlated to silicon behavior.

Education Requirements

Preferred: Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. The posting also references 2 or more years of relevant industry experience as preferred. (If no degree, equivalent practical experience is acceptable.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.