SoC Physical Design Verification Engineer

Job Title

SoC Physical Design Verification Engineer

Role Summary

Drive full-chip physical verification and signoff for advanced-node SoCs to ensure manufacturable, high-quality silicon. Work across RTL, physical design, CAD, packaging, and foundry interfaces to close DRC/LVS/ERC and related checks and to resolve tapeout issues.

This is a hybrid role based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.

Experience Level

Senior-level — typically 7–14 years of hands-on CPU/IP/SoC physical verification and tapeout experience.

Responsibilities

The main responsibilities focus on achieving signoff-quality mask data and enabling successful tapeouts.

• Lead physical verification closure for full-chip designs (DRC, LVS, ERC, PERC, Antenna, DFM).
• Run and debug verification flows using industry PV tools and report results to cross-functional teams.
• Automate verification flows and checks using scripting (Python, TCL) and optimize runtime/turnaround.
• Coordinate with RTL, PD, CAD, packaging, and foundry contacts to resolve violations and manufacturability issues.
• Participate in signoff planning, signoff reviews, and tapeout readiness activities.
• Perform reliability analysis related to IR drop, electromigration (EM), and ESD considerations.
• Mentor junior engineers and contribute to development of PV methodologies and scalable automation.

Requirements

Must-have skills and experience for the role.

• 7–14 years of hands-on CPU/IP/SoC physical verification and tapeout closure experience.
• Strong experience with industry PV tools and flows (Calibre, ICV, Pegasus, Foundry Checker, Innovus, or equivalent).
• Proven expertise in DRC, LVS, ERC, PERC, Antenna checks, and DFM verification practices.
• Experience with advanced-node challenges (7nm, 5nm, 3nm) and FinFET design implications.
• Scripting proficiency for automation and flow optimization (Python, TCL).
• Practical knowledge of ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
• Strong debugging skills and ability to drive closure across multiple engineering teams and foundry points of contact.

Education Requirements

BS or MS in Engineering (Electrical, Electronics, or a related field) is stated as the preferred academic background.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.