SoC Physical Design Senior Manager, HBM

Job Title

SoC Physical Design Senior Manager, HBM

Role Summary

Lead a team in the Heterogeneous Integration Group (HIG) responsible for physical implementation and signoff of advanced HBM SoC logic/base-die designs from netlist to GDSII. Work cross-functionally with RTL, verification, DFT, IP providers, packaging, and manufacturing to meet PPA and signoff requirements.

This is a hands-on management role with responsibility for project resourcing, execution of block and top-level physical design, timing closure, signoff, and continuous improvement through automation and AI-driven workflows.

Experience Level

Senior - minimum 15 years of related experience (as indicated in the posting).

Responsibilities

Key delivery and people-management responsibilities for HBM base-die SoC physical design and signoff.

• Recruit, develop, and mentor physical design and verification engineers.
• Plan and prioritize project resourcing and timelines to meet aggressive delivery schedules.
• Drive physical implementation: floorplanning, placement, CTS, routing, and physical optimization for PPA.
• Lead timing closure across multi-mode/multi-corner (MMMC) scenarios and coordinate with RTL, architecture, and STA/signoff teams.
• Ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate complex IP (controllers, NOCs, interfaces, MBIST/DFT logic, PHY-adjacent logic) with focus on timing and power integrity.
• Perform/coordinate physical signoff: DRC/LVS, IR drop/EM, parasitic extraction awareness, and timing signoff.
• Support tapeout execution, ECO flows, signoff reviews, and post-silicon debug correlation.
• Identify flow gaps and improve productivity through scripting, automation, and methodology development.
• Drive development and adoption of agentic AI and LLM-driven workflows for PD/verification tasks.

Requirements

Must-have technical skills and experience for successful performance in the role. Preferred items listed separately.

• Strong SoC physical design experience implementing designs from netlist to GDSII on advanced nodes and complex SoCs.
• Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals, clocking, SDC constraints, and closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery practices (UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification and signoff concepts (DRC, LVS, ERC, parasitic extraction, signoff handoff quality).
• Exposure to hierarchical physical design, top-level assembly/partitioning, and large-scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
• Proven tapeout history on advanced foundries (e.g., TSMC) and full-cycle SoC development flow understanding.
• Ability to work in a global, cross-functional environment with strong communication and debugging skills.
• Experience implementing AI flows and using agentic AI and LLMs.

Nice-to-have:

• Experience with HBM- or DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.
• Proven ability to mentor and develop junior engineers.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (preferred).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.