SoC Physical Design Lead

Job Title

SoC Physical Design Lead

Role Summary

Lead the end-to-end physical implementation of high-performance, low-power SoCs to meet PPA (power, performance, area) and schedule targets. Act as a technical authority across multiple programs, collaborating with RTL, architecture, CAD, verification and cross-functional teams to drive sign-off and tapeout readiness.

Experience Level

Senior — 15+ years of relevant physical design experience preferred.

Responsibilities

Accountable for delivering physical design results and guiding teams on implementation and sign-off.

• Own floorplanning, placement, CTS, routing, timing closure, and overall PnR flow for SoCs.
• Define and optimize place-and-route strategies for advanced nodes (e.g., 5nm/3nm/2nm) to balance PPA.
• Establish sign-off criteria, waiver processes, and publish risk burndown and mitigation plans for tapeout-critical paths.
• Introduce techniques for congestion management, timing optimization, and power integrity.
• Partner with RTL, architecture, CAD, and verification teams to resolve integration and design challenges.
• Influence design partitioning, interface planning, hierarchical strategies, and ECO readiness gates to manage schedule risk.
• Lead technical reviews, provide consultative input to management, and mentor engineers.
• Work with design teams on area and floorplan refinement, timing targets, pre-silicon bug resolution, and PPA sign-off.

Requirements

Core technical skills, tooling experience, and leadership capabilities required for the role.

• Must-have: Deep expertise in physical design flows (PnR), timing closure, clock tree synthesis, routing, and floorplanning for high-performance SoCs.
• Must-have: Experience with EDA tools such as Innovus, Fusion Compiler/ICCompiler2, PrimeTime, or equivalent sign-off and PnR tools.
• Must-have: Strong record of meeting PPA and schedule targets on advanced-node designs and driving tapeout readiness.
• Must-have: Excellent communication, presentation, and cross-team collaboration skills; experience briefing executives and mentoring engineers.
• Preferred: Foundational SoC architecture experience in one or more areas: CPU/GPU, memory subsystem, fabrics, coherency, multimedia, I/O, clocks & resets.
• Preferred: Proven ability to influence design partitioning, manage ECO cycles, and implement congestion/timing mitigation techniques.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. The posting does not state an explicit "or equivalent experience" clause.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.