SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS)

Job Title

SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS)

Role Summary

Implement advanced HBM SoC logic/base-die designs from netlist to GDSII as part of the Heterogeneous Integration Group (HIG). Work with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing to deliver PPA targets and signoff-ready deliverables.

Experience Level

Senior level. The role expects an experienced engineer; the posting indicates a preferred minimum of 15 years in a related field (typical senior roles are 7+ years).

Responsibilities

Core responsibilities include implementation, signoff, and cross-team integration for complex SoC designs.

• Own physical implementation for SoC blocks and/or top-level: floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure across multi-mode/multi-corner (MMMC) scenarios; coordinate with RTL, architecture, and STA/signoff teams.
• Ensure robust clocking/reset strategy, power architecture, and SoC integration compliance.
• Integrate complex IP (controllers, NOC, MBIST/DFT, PHY-adjacent logic) with focus on timing and power integrity.
• Perform or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff; resolve violations efficiently.
• Collaborate with packaging, assembly, test, probe, and manufacturing to address manufacturability and quality.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and post-silicon debug correlation.
• Identify flow gaps and improve productivity via scripting, automation, and methodology improvements.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

Must-have:

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced process nodes and complex designs.
• Proficiency with industry EDA tools (examples: Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Experience with power intent and power delivery considerations (UPF/CPF concepts, power-grid planning, power-gating implications).
• Exposure to hierarchical physical design, top-level assembly, partitioning, and large-scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation techniques.
• Proven tapeout history on advanced foundries (e.g., TSMC) and familiarity with full-cycle SoC development flows.
• Strong scripting/automation skills (Python, TCL, Perl, and/or shell).

Nice-to-have:

• Experience with HBM or DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the preferred qualifications).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.