SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team
QualcommJob Title
SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team
Role Summary
Lead physical design activities for complex SoC subsystems on advanced process nodes within the HM PD team. Deliver place-and-route, sign-off convergence and PPA improvements while coordinating with IP, RTL and verification teams.
Responsible for driving implementation strategy, resolving timing and power closure issues, and guiding a small team or subsystem-level design effort to production-quality sign-off.
Experience Level
Senior-level role. Typical experience profile: approximately 6 to 15 years working in physical design for ASIC/SoC; experience managing complex subsystems and small teams.
Responsibilities
Accountable for physical design delivery and technical leadership across subsystem implementations.
- Lead synthesis, place-and-route (PnR) and sign-off convergence activities.
- Perform Static Timing Analysis (STA) and implement sign-off optimizations.
- Drive low-power implementation (UPF, multi-voltage domains, power gating) and verification of power intent.
- Integrate IP blocks and resolve integration issues affecting PPA and timing closure.
- Define and enforce ASIC physical design flows and methodology across the subsystem.
- Analyze circuit and device-level issues relevant to deep sub-micron technologies and advanced nodes.
- Develop and apply automation to improve PPA and accelerate design closure.
- Mentor and coordinate small teams to meet delivery milestones and quality targets.
Requirements
Must-have technical skills and experience for successful performance in this role.
- 6+ years of hands-on physical design experience (typical range 6–15 years) focused on SoC/subsystem implementations.
- Proven experience with synthesis, PnR, STA and sign-off optimization techniques.
- Experience meeting demanding power, performance, and area (PPA) targets on complex subsystems and SoCs.
- Working knowledge of low-power implementation flows including UPF, multi-voltage domains and power gating.
- Familiarity with ASIC design flows, physical verification and IP integration processes.
- Understanding of circuit design and device physics relevant to deep sub-micron/advanced technology nodes.
- Practical experience building or using automation to improve PPA and design turnaround.
- Experience leading or managing small technical teams or subsystem efforts.
Education Requirements
Candidates typically hold a Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering or a related field. Qualification-to-experience mappings in the posting: Bachelor's degree with ~6+ years' related experience, Master's degree with ~5+ years' related experience, or PhD with ~4+ years' related experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
