SoC Limits Management Architect
QualcommJob Title
SoC Limits Management Architect
Role Summary
Senior architect on the HW power team responsible for defining SoC limits-management architecture that balances performance with electrical, thermal and reliability constraints. You will bridge hardware IP, firmware policies and system software, working with architects, designers and software teams from early product definition through post-silicon validation.
Experience Level
Senior - the posting expects substantial industry experience. The role specifically cites ~15+ years in Power Management/Low-Power Design; the posting also includes alternative degree-tied thresholds (see Education Requirements).
Responsibilities
Design and drive a system-level limits management solution and coordinate cross-functional implementation.
- Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize mitigation features such as power telemetry, estimators, and droop detectors across IP and hardware blocks.
- Drive long-term evolution of sensing IPs (voltage, current, temperature) and trigger mechanisms to address increasing current densities.
- Specify real-time telemetry requirements and performance-impact profiles for mitigation strategies.
- Oversee post-silicon validation to ensure physical silicon behavior matches architectural intent and make ROI-based feature tradeoffs.
- Contribute to product definition through early involvement in the product lifecycle and coordinate with software and hardware teams for integration.
Requirements
Must-have technical experience and capabilities for successful performance in this role.
- Extensive experience in power management or low-power design/methodology; posting emphasizes ~15+ years in this domain.
- Proven track record across the full product delivery cycle: architecture definition through post-silicon productization.
- Practical experience with low-power architectures and advanced power-optimization techniques.
- Experience specifying telemetry and detection/mitigation mechanisms (power telemetry, estimators, droop detection, real-time monitoring).
- Ability to define architecture and micro-architecture and to collaborate with hardware IP teams and system software groups.
Nice-to-have
- Experience in peak power management, power budgeting, in-rush current handling, PDN droop detection/mitigation, and adaptive clock distribution.
- Experience with aging/process monitors, power-aware floorplanning, battery technologies, concurrency management, thermal management, and AI-related power considerations.
- Strong influencing and leadership skills to drive cross-functional roadmaps and ROI-based decisions.
Education Requirements
Posting references degrees in science/engineering fields: Bachelor's, Master's or PhD in Engineering/Computer Engineering/Electrical Engineering/Computer Science or related technical fields; also allows "equivalent practical experience." Degree-year guidance appears in two places: one section lists degree-tied thresholds (Bachelor's +6 years, Master's +5 years, PhD +4 years) while another section emphasizes ~15+ years of industry experience in Power Management as the expected level.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
