SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)
QualcommJob Title
SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)
Role Summary
Lead system-level validation for SoC infrastructure-NoC, power and performance-on Qualcomm's AI accelerator and compute platforms. Work spans pre-silicon emulation and post-silicon validation, developing scalable test content, automation, and cross-layer debugs across hardware and software.
Experience Level
Senior (Staff level). The role expects experienced engineers with significant hands-on silicon validation or platform bring-up background; posting references 7+ years in silicon validation or platform bring-up.
Responsibilities
Accountable for planning, executing, and communicating performance and power validation for SoC infrastructure.
- Define and execute performance and power validation plans; include power-performance trade-off analysis.
- Analyze SOC bandwidth, QoS, latency and throughput; stress interconnects for coverage.
- Correlate pre-silicon models, emulation results, and silicon measurements.
- Evaluate AI inference and training workloads for throughput, latency, memory bandwidth, and power-efficiency.
- Develop performance characterization methodology, benchmarks, KPIs, dashboards, and reports for leadership.
- Debug complex HW/SW interactions across CPU, DDR, GPU, multimedia, and peripherals.
- Author drivers, bare-metal test content, and automation to validate system features at scale.
Requirements
Must-have technical skills and domain expertise; preferred items noted where applicable.
- Deep knowledge of interconnect architectures (NoC, AXI, AHB) and ability to write traffic generators/stress programs.
- Expertise in FIFO designs and their performance/functional trade-offs.
- Strong understanding of memory hierarchy, cache coherency/consistency, synchronization, and full-system concurrency.
- Familiarity with CPU and DDR concepts, system low-power modes, dynamic clock/voltage scaling, and interrupt architecture.
- Experience with debug architectures and tools (JTAG, kernel debuggers) and creating state-dump/debug scripts.
- Experience with performance-monitoring architectures (perfmon), telemetry data, and HW/SW co-optimization.
- Proven ability to debug complex hardware/software issues and drive cross-functional correlation activities.
- Proficient in embedded software: C, C++, Python, and assembly; experience designing drivers and test content.
- Ability to create performance dashboards, technical reviews, and communicate results to cross-functional stakeholders.
- Preferred: familiarity with AI/ML accelerators, tensor ops, matrix multiplication, transformer models, and system-level bring-up.
Education Requirements
Degree required: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Posting lists alternative minimums: Bachelor's + 4+ years relevant ASIC design/verification/validation/integration experience; OR Master's + 3+ years; OR PhD + 2+ years.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
