SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff

Job Title

SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff

Role Summary

Member of the System Validation & Emulation (SVE) team responsible for system-level validation of Qualcomm SoCs in pre- and post-silicon phases. The role focuses on content quality, scalable validation frameworks, and cross-boundary HW/SW debug to validate performance, power, and system functionality.

Experience Level

Senior (Staff). The posting targets experienced engineers; typical experience expectations are multiple years in silicon validation, platform bring-up, or equivalent ASIC/system validation roles.

Responsibilities

Accountable for planning, implementing, and scaling performance and power validation across SoC domains.

• Develop and execute performance and power validation plans; factor Performance-Power trade-offs.
• Analyze SOC bandwidth, QoS, latency and throughput; stress interconnect transactions for coverage.
• Correlate results between pre-silicon models, emulation platforms, and silicon measurements.
• Evaluate AI inference/training workloads for throughput, latency, memory bandwidth, and power-efficiency.
• Create performance dashboards, technical reports, and present findings to leadership and cross-functional teams.
• Design and implement drivers and test content; develop scalable automation for validation.
• Debug complex hardware and software interactions across full-system stacks; use JTAG and kernel debug facilities.
• Contribute to methodology for performance characterization, benchmarking, and KPI tracking across product generations.

Requirements

Must-have skills and experience for successful performance/power validation of SoC platforms. Education requirements are summarized below in the Education Requirements section.

• Experience: 5+ years in silicon validation, platform bring-up, or equivalent ASIC/system validation experience.
• Interconnects: Deep knowledge of NoCs, AXI, AHB; ability to write programs to exercise upstream/downstream transactions and stress coverage.
• Memory & caches: Understanding of memory hierarchy, cache coherency/consistency, synchronization, semaphores, and full-system concurrency.
• CPU, DDR & peripherals: Strong grasp of CPU architecture, DDR concepts, multimedia, GPU and peripheral interactions.
• Low power: Knowledge of system low-power modes, dynamic clock/voltage scaling, and static/leakage/dynamic power fundamentals.
• Debug & telemetry: Experience with debug architectures, JTAG, state-dump scripts, performance counters (Perfmon), and telemetry data analysis.
• Software & tooling: Embedded systems experience and proficiency in C, C++, Python and assembly; driver and test content implementation experience.
• Problem solving: Strong logical reasoning and demonstrated ability to debug complex HW/SW issues and drive cross-team resolution.

Nice-to-have:

• Familiarity with AI/ML accelerator architecture, tensor operations, matrix multiplication, and transformer workloads.
• Experience with system-level debug, silicon bring-up, and benchmarking methodologies across product generations.

Education Requirements

Degrees: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Science, Engineering, or a related technical field are referenced. Qualcomm's minimum-qualification mapping in this posting: Bachelor's +4 years, Master's +3 years, or PhD +2 years of relevant ASIC design/verification/validation/integration experience. (The posting also lists a separate 5+ years experience expectation for silicon validation/platform bring-up.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.