SoC Engineering Senior Engineer

Job Title

SoC Engineering Senior Engineer

Role Summary

Design and implement RTL for SoC subsystems as part of the Solutions group. Work with verification, DFT, and physical design teams to deliver production-quality blocks that meet timing, area, and power targets for customer silicon.

Collaborate across global teams on RTL development, synthesis readiness, and integration into larger SoC projects targeting automotive, aerospace, defense, and high-performance computing products.

Experience Level

Senior-level. The posting requests 3–4 years of hands-on ASIC or FPGA RTL design, implementation, and debug experience.

Responsibilities

Primary responsibilities include RTL development, quality checks, and cross-team collaboration to achieve timing-closed designs.

• Write and review Verilog, SystemVerilog, or VHDL RTL for state machines, pipelines, FIFOs, memory controllers, and block-level designs.
• Run RTL quality checks (linting, CDC/RDC analysis, synthesis) and prepare designs for handoff to physical design.
• Collaborate with verification engineers to debug testbench failures and close coverage gaps.
• Work with physical design teams to resolve timing issues and support timing closure from netlist through signoff.
• Implement and verify standard interfaces such as AXI, APB, AHB, I2C, and SPI within SoC subsystems.
• Automate repetitive tasks using scripting (Python, Tcl, shell) to improve the design flow.
• Participate in design reviews and communicate design decisions and trade-offs to global stakeholders.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• 3–4 years of hands-on ASIC or FPGA RTL design, implementation, and debug experience.
• Strong proficiency in Verilog, SystemVerilog, or VHDL for registers, pipelines, state machines, memories, and FIFOs.
• Practical knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and timing closure.
• Experience with industry-standard tools: simulators, lint checkers, CDC/RDC tools, synthesis tools, and static timing analysis.
• Solid understanding and implementation experience with AXI, APB, AHB, I2C, and SPI protocols.
• Ability to read micro-architecture specifications, identify ambiguities, and produce clean, synthesis-friendly RTL.
• Good communication skills for collaborating across time zones and with cross-functional teams.

Nice-to-have:

• Experience with complex protocols such as PCIe, DDR, or Ethernet.
• Familiarity with SystemVerilog assertions, C++ or Python for verification, low-power methodologies (UPF), DFT, formal tools, Git workflows, or AI-assisted engineering tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.