SoC Engineering Principal Engineer

Job Title

SoC Engineering Principal Engineer

Role Summary

Lead static timing analysis (STA) signoff and timing/power closure for advanced-node SoC designs. The role focuses on delivery of tape-out quality timing and power closure flows, tool optimization, and automation while collaborating with cross-functional global teams.

Expect to define and validate timing constraints, drive STA and power analyses, and mentor engineers to improve flows and methodology.

Experience Level

Senior-level. Requires 12+ years of relevant experience in static timing analysis, timing/power closure, and working with advanced process nodes (7nm/5nm/3nm).

Responsibilities

Primary responsibilities include ownership of signoff STA and timing closure, tool usage, and flow automation.

• Own and drive signoff static timing analysis and timing closure for advanced process nodes to support successful tape-outs.
• Perform STA, power analysis, and correlate results with synthesis and implementation flows.
• Develop, validate, and maintain timing constraints at block and full-SoC levels.
• Generate timing and power ECOs and support closure under aggressive schedules.
• Use and optimize Synopsys EDA tool flows for timing and power (signoff and implementation tools).
• Develop and maintain automation and analysis scripts to streamline flows and improve repeatability.
• Collaborate with cross-functional and geographically distributed teams to resolve design and schedule issues.
• Mentor and guide junior engineers; contribute to methodology and flow improvements.

Requirements

Technical must-haves and relevant experience; degree requirements are listed separately below.

• Must-have: Extensive hands-on experience in static timing analysis, constraints development, validation, and timing/power ECO generation for both block and full-chip designs.
• Must-have: Proficiency with Synopsys signoff tools such as PrimeTime, PT-PX, PrimePower, PrimeClosure, and Tweaker.
• Must-have: Strong scripting and automation skills (Python, PERL, TCL or similar).
• Must-have: Experience with advanced-node designs (7nm/5nm/3nm) and familiarity with high-frequency and low-power design considerations.
• Nice-to-have: Working experience with Fusion Compiler, Design Compiler, Formality, StarRC, and understanding of physical implementation impacts (parasitic extraction, clock tree structure).
• Nice-to-have: Formal verification exposure and synthesis/implementation tool correlation experience.

Education Requirements

Bachelor's or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.