SOC Engineer - Synthesis & Timing

Role Overview

The SOC Engineer at Synopsys in Ho Chi Minh City will work directly on ASIC/SOC projects, focusing on synthesis, timing closure, and digital design flow optimization.

Position Summary

As an SOC Engineer, you will be responsible for the development and execution of design solutions using Synopsys EDA tools and IP. You will contribute to both turnkey projects and offer insights as a trusted advisor to customers, helping to implement innovative solutions independently and efficiently.

Experience Level

The ideal candidate will possess 2 to 4 years of relevant experience, showcasing strong skills in ASIC/SOC design and timing implementation.

Key Responsibilities

• Conduct synthesis and timing analysis for SOC projects.
• Perform Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checks.
• Utilize tools like PTPX, STA, and GCA for effective design verification.
• Collaborate with cross-functional teams to enhance tool and IP solutions.
• Develop technical solutions to optimize project outcomes.

Position Requirements

The candidate should have a solid understanding of ASIC/SOC design, particularly focusing on synthesis and timing processes. Experience with advanced process nodes (under 12nm) and low-power design techniques is an advantage. Familiarity with scripting languages such as TCL, Perl, or Python is important, alongside effective communication skills in English.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering or a related field is required for this position.