SoC Design Verification Engineer — Pre-Silicon/Post-Silicon Verification

Job Title

SoC Design Verification Engineer — Pre-Silicon/Post-Silicon Verification

Role Summary

Join the Pre‑Silicon and Post‑Silicon SoC Verification team to verify next‑generation SoCs for mobile, AI, HPC, and cloud products. The role covers pre‑silicon simulation, emulation/acceleration, and post‑silicon bring‑up and validation.

Engineer‑level contributors execute verification tasks and debug under technical guidance; Senior Engineers own feature verification, lead cross‑team debug, and improve methodology and automation.

Experience Level

Hiring Engineer and Senior Engineer levels. Engineer: typically 2+ years of relevant design verification/validation/SoC debug experience. Senior Engineer: typically 4+ years with demonstrated ownership of complex verification or silicon bring‑up deliverables.

Responsibilities

Work across pre‑silicon and post‑silicon flows to plan, implement, verify, and close verification for SoC features and subsystems.

• Develop and execute verification plans for SoC, subsystem, and IP features across pre‑silicon and post‑silicon phases.
• Build, enhance, and maintain SystemVerilog/UVM, C/C++, emulation, and acceleration verification environments.
• Create directed, constrained‑random, stress, performance, power, and system‑level tests to validate architecture and real use cases.
• Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics for verification closure.
• Debug RTL, testbench, emulation, firmware, ATE/vector, and silicon bring‑up issues using logs, waveforms, traces, and hardware debug data.
• Support post‑silicon validation, silicon characterization, ATE pattern debug, failure triage, and correlation between simulation, emulation, and silicon results.
• Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.
• Participate in architecture, micro‑architecture, design, validation, and test‑plan reviews to capture verification and bring‑up requirements early.
• Engineer level: execute assigned verification tasks, maintain regressions, and contribute to coverage and bring‑up activities.
• Senior level: own feature/subsystem verification from plan to closure, lead debug across teams, mentor engineers, and drive methodology/automation improvements.

Requirements

Must‑have technical skills and demonstrated verification experience.

• Practical verification experience: Engineer (typically 2+ years), Senior (typically 4+ years) in design verification, validation, or SoC debug.
• Strong knowledge of SystemVerilog, UVM, C/C++, assertion‑based verification, and coverage‑driven verification.
• Experience developing or using verification environments from spec/architecture through signoff, including regressions, coverage, and debug flows.
• Understanding of post‑silicon validation concepts: bring‑up, ATE/vector debug, failure triage, HW/SW interaction, and pre/post correlation.
• Solid understanding of computer architecture, digital design fundamentals, and SoC integration concepts.
• Strong communication, collaboration, ownership, and problem‑solving skills.

Nice‑to‑have:

• Experience with CPU/subsystem/full‑chip SoC verification, cache coherency protocols (ACE, CHI, CXL), and memory subsystems (DDR, LPDDR, HBM).
• PCIe, CXL, Ethernet, networking, or other high‑speed interface verification experience.
• Experience with AI/ML accelerators, security, RAS, performance, or power feature verification.
• Post‑silicon bring‑up, silicon validation (Trace32), ATE pattern debug, shmoo/debug analysis, or failure triage experience.
• Familiarity with emulation/acceleration platforms (Veloce, Palladium, ZeBu) and correlation between simulation, emulation, and silicon.
• Experience with Portable Stimulus, formal verification, power‑aware verification, firmware‑driven validation, or HW/SW co‑verification.
• Proficiency in Python, Perl, shell scripting, or similar for regression automation, debug, and data analysis.
• For Senior candidates: demonstrated leadership in feature closure, cross‑team coordination, mentoring, and communicating technical risks.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.