SOC Design Verification Engineer

Job Title

SOC Design Verification Engineer

Role Summary

Responsible for functional verification of an integrated SoC to ensure the design meets microarchitecture and specification targets. Work on developing verification plans, scalable testbenches, and verification environments at block, subsystem, and full-chip levels.

Collaborate with architects, RTL developers, postsilicon and physical design teams to find, debug, and resolve pre-silicon issues; contribute to verification infrastructure, emulation, simulation, security testing, and coverage improvement.

Experience Level

Entry-level / College Graduate. Typical background: 0–3 years in verification with at least 1+ years pre-silicon verification and 1+ years SystemVerilog/UVM experience.

Responsibilities

Primary responsibilities include verifying SoC functional correctness, developing test plans and environments, and collaborating across teams to close verification gaps.

• Define and develop scalable, reusable block, subsystem, and SoC verification plans and testbenches.
• Implement and execute tests using SystemVerilog/UVM, emulation, and simulation to validate functionality, power, and performance.
• Replicate, root-cause, and debug design issues in presilicon environments; drive fixes and regression runs.
• Document test plans and results; lead technical reviews with design and architecture teams.
• Integrate security verification activities into test plans and regressions.
• Maintain and improve verification infrastructure, methodologies, and coverage, and incorporate postsilicon learnings into presilicon plans.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 1+ years SystemVerilog and UVM experience.
• Must-have: 2+ years Python for test automation.
• Must-have: Proficiency in C/C++ and scripting (Perl, Tcl, Shell) — ~6+ months exposure.
• Must-have: 1+ years pre-silicon functional verification experience.
• Must-have: Linux/Unix and version control experience (Git, Perforce) — ~6+ months.
• Must-have: Regression testing, CI/CD pipelines experience — ~6+ months.
• Must-have: Familiarity with security verification methodologies — ~6+ months.
• Nice-to-have: Experience with simulation tools (VCS, Xcelium, Questa), formal tools, and coverage analysis.
• Nice-to-have: Constrained-random and assertion-based verification experience.
• Nice-to-have: Knowledge of x86 SoC or equivalent architectures, AMBA protocols (AXI/AHB/APB), memory subsystems, cache coherency, power management, and high-speed interfaces (PCIe, DDR, USB, Ethernet).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science is required per the posting. (Degree requirement: Bachelors or Masters in EE, CE, and/or CS.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.