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SOC Design Implementation Engineer

Qualcomm
October 20, 2026
Full-time
On-site
Hyderabad, Telangana, India
Physical Design Jobs, Level - Entry or Early Career

Job Title

SOC Design Implementation Engineer

Role Summary

Work on SoC design implementation with focus on synthesis, timing closure, DFT, gate-level validation and signoff. The role is part of the Hardware Engineering team and collaborates with Design, DFT and Physical Design teams to meet performance, power, area and timing targets for ASIC/SoC projects.

Experience Level

Entry-level. Typical minimum experience ranges from 1–2+ years of relevant hardware/implementation experience depending on degree (see Education Requirements).

Responsibilities

Key day-to-day responsibilities include implementation, verification and timing signoff tasks for SoC designs.

  • Perform RTL synthesis to meet performance, power and area objectives.
  • Insert and validate DFT (MBIST, SCAN) and configure test-mode timing constraints.
  • Run static low-power checks on gate-level netlists.
  • Verify logic equivalence between RTL and gate-level representations.
  • Set up and execute signoff static timing analysis (STA) and ECO flows to achieve timing closure.
  • Perform timing analysis using STA tools and debug timing/constraints issues.
  • Collaborate with Design, DFT and Physical Design (PD) teams during closure and validation.

Requirements

Must-have technical skills and experience for successful candidates.

  • Practical experience with RTL-to-gates implementation flows and synthesis tools.
  • Hands-on experience with DFT flows, MBIST and SCAN insertion and validation.
  • Experience with static timing analysis and signoff flows; ability to run and interpret STA results.
  • Experience performing logic equivalence checks (RTL-to-gates, gates-to-gates).
  • Ability to debug constraints, timing issues and perform ECOs to resolve closure problems.
  • Experience running low-power verification checks on gate-level netlists.
  • Effective collaboration skills with cross-functional teams (Design, DFT, PD).
  • Nice-to-have: prior exposure to FPGA bring-up, test systems or ASIC bring-up and validation workflows.

Education Requirements

Minimum qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field plus 2+ years of hardware engineering experience; OR Master's degree in those fields plus 1+ year of hardware engineering experience; OR PhD in those fields.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-10-19