SOC Design Engineer

Job Title

SOC Design Engineer

Role Summary

Design and deliver digital RTL and micro-architecture for ASIC subsystems, with a focus on power control systems and implementation on advanced process nodes. The role involves end-to-end VLSI development activities including architecture, RTL design, integration, verification interaction, synthesis convergence, and collaboration with PD/DFT/SW teams.

Work with multi-site engineering teams across locations to integrate complex subsystems into SoC products and support design closure and post-silicon activities.

Experience Level

Mid-level - typically 5–8 years of relevant digital front-end ASIC design experience.

Responsibilities

Primary responsibilities include RTL design, micro-architecture implementation, integration, and cross-team collaboration.

• Develop digital RTL (Verilog/SystemVerilog) and implement micro-architecture for complex subsystems.
• Integrate and deliver subsystems into SoC designs; ensure multi-clock and multi-power-domain correctness.
• Collaborate with Systems, Verification, SoC, Software, Physical Design (PD) and DFT teams to reach design goals.
• Analyze tool reports and run EDA tools such as SpyGlass, lint/CDC checks, synthesis tools, DC-Compiler, PrimeTime, and simulators.
• Drive design convergence with synthesis and PD teams and respond to waiver or report findings.
• Work with multi-site leads across engineering locations to coordinate deliverables and schedules.
• Participate throughout the VLSI development cycle from architecture through post-silicon debug.

Requirements

Must-have technical skills and experience for successful candidates.

• 5+ years strong experience in digital front-end ASIC design (experience range typically 5–8 years).
• Expert RTL coding skills in Verilog, VHDL or SystemVerilog for complex designs with multiple clock and power domains.
• Practical knowledge of low-power design methodology, UPF, and power-domain crossing techniques.
• Experience with bus protocols such as AHB, AXI, SPMI, I2C and SPI.
• Experience running and responding to SpyGlass lint and CDC checks; creating waivers.
• Familiarity with formal verification flows (e.g., Cadence LEC) and RTL-to-GDSII flow to coordinate with DFT and PD teams.
• Proficiency in scripting (Perl, TCL) for automation and flow support.
• Nice-to-have: post-silicon debug experience.

Education Requirements

Bachelor's degree in Science, Engineering, or related field with 4+ years relevant ASIC design/verification experience; OR Master’s degree in Science, Engineering, or related field with 3+ years; OR PhD in Science, Engineering, or related field with 2+ years. Fields referenced: science and engineering disciplines or related technical fields.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.