SOC Design Engineer

Job Title

SOC Design Engineer

Role Summary

Design and implement digital ASIC blocks and subsystems for power control and other SoC functions. Work across architecture, RTL design, verification, synthesis, physical design (PD) and validation to deliver silicon-ready IP on advanced process nodes.

Position sits in a multi-site engineering team collaborating with systems, verification, SoC, software, PD and DFT teams to integrate and optimize designs for performance, power and quality.

Experience Level

Mid-level: typically 5–8 years of relevant ASIC digital design experience (experience guidance from the posting). Candidates with fewer years but equivalent domain experience may be considered.

Responsibilities

Primary engineering responsibilities include architecture-to-RTL implementation, integration and cross-team coordination.

• Develop microarchitecture and implement RTL (Verilog/SystemVerilog/VHDL) for complex subsystems.
• Integrate subsystems into SoC and deliver design blocks to downstream teams.
• Collaborate with Systems, Verification, SoC, SW, PD and DFT teams to resolve issues and converge on design goals.
• Analyze reports and run RTL/STA/tools such as Spyglass, synthesis tools, DC-Compiler and PrimeTime.
• Support design convergence activities with synthesis, timing closure and power optimization.
• Implement low-power design techniques and handle multi-clock and multi-power-domain designs including power domain crossings.
• Participate in post-silicon debug and validation activities as needed.

Requirements

Technical skills and domain experience required or strongly preferred.

• Must-have: Strong digital front-end ASIC design experience and RTL coding expertise in Verilog/SystemVerilog/VHDL for complex designs.
• Must-have: Experience with multi-clock and multi-power-domain designs and low-power design methodologies (UPF familiarity).
• Must-have: Practical experience with CDC checking and linting tools (e.g., Spyglass) and waiver creation.
• Must-have: Familiarity with standard bus protocols (AHB, AXI, SPMI, I2C, SPI) and RTL-to-GDS flow interactions with PD and DFT teams.
• Must-have: Experience using synthesis, static timing analysis and simulation flows (DC-Compiler, PrimeTime or equivalents).
• Must-have: Scripting skills (Perl, TCL) for automation and tool flows.
• Nice-to-have: Experience with formal verification tools (e.g., Cadence LEC) and post-silicon debug.

Education Requirements

Bachelor's degree in Science, Engineering or related field plus 4+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering or related field plus 3+ years; OR PhD in Science, Engineering or related field plus 2+ years. The posting describes degree-based experience alternatives rather than specific certifications.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.