SoC Debug Engineer

Job Title

SoC Debug Engineer

Role Summary

Early-career FPGA/RTL engineer contributing to a proprietary JTAG-based SoC debug tool used for silicon bring-up, validation, and debugging. The role sits within a silicon debug solutions organization and supports pre- and post-silicon validation teams.

Work involves FPGA RTL design and verification, lab bring-up, and close collaboration with software, validation, and hardware teams to enable and improve debug and validation capabilities.

Experience Level

Entry-level / Early-career. Candidates with a Bachelor’s degree are expected to have a minimum of 2 years of relevant experience; candidates with a Master’s degree may be considered with no prior professional experience.

Responsibilities

Primary responsibilities include FPGA RTL development, verification, and integration to support SoC debug and validation.

• Implement and maintain FPGA RTL (VHDL/Verilog/SystemVerilog) to enable and enhance debug/validation features.
• Integrate FPGA designs with JTAG/TAP interfaces and debug transport/control logic.
• Write and run simulations; develop testbenches and automated checks to validate functional correctness.
• Debug RTL and hardware issues using waveforms, assertions, and on-hardware instrumentation (e.g., ILA/SignalTap).
• Contribute to FPGA build flows (synthesis/place-and-route/bitstream) and improve reproducibility and resource utilization.
• Collaborate with software, validation, and hardware teams to clarify requirements and support internal users.
• Develop FPGA-based test/demo environments and automation for builds, regression testing, and lab workflows.

Requirements

Must-have skills and constraints required to be considered for the role.

Must-have:

• Practical FPGA/RTL development experience (including internships, co-ops, or substantial academic/personal projects).
• Ability to read, modify, and write RTL in VHDL and/or Verilog/SystemVerilog.
• Experience with RTL simulation and basic testbench usage.
• Advanced English proficiency (reading and communication).
• Unrestricted, permanent right to work in Mexico (no visa sponsorship available).

Nice-to-have:

• Familiarity with Git and standard software development practices (branching, code reviews, documentation).
• Exposure to FPGA vendor toolchains (e.g., Xilinx Vivado, Intel Quartus) and constraint formats (XDC/SDC).
• Knowledge of RTL verification concepts (testbenches, assertions/SVA; UVM is a plus).
• Familiarity with JTAG/TAP, boundary scan, and debug/bring-up flows.
• Experience debugging FPGA designs in hardware (e.g., ILA/SignalTap) and basic scripting (Python/Tcl/Bash) for automation.
• Understanding of clock-domain crossing, reset strategy, timing/performance tradeoffs, and common interfaces (AXI, PCIe, Ethernet).

Education Requirements

Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electronics Engineering, or a related field. Candidates with a Bachelor’s degree should have a minimum of 2 years of relevant experience; candidates with a Master’s degree may be considered with no prior professional experience. Relevant experience may include industry work, internships/co-ops, substantial academic projects, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.