SoC Compute/Memory Subsystem Architect

Job Title

SoC Compute/Memory Subsystem Architect

Role Summary

The SoC Compute/Memory Subsystem Architect will define and drive the architecture of compute complexes, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms. The role sits in a networking architecture team focused on high-performance networking silicon for hyperscale data centers, cloud infrastructure, and AI workloads.

This senior individual contributor will optimize system-level performance, scalability, power efficiency, and programmability and will coordinate closely with networking, storage, accelerator, firmware, and validation teams to deliver balanced SoC solutions.

Experience Level

Senior level — requires 10+ years of relevant experience in SoC/CPU/memory subsystem architecture.

Responsibilities

Accountable for end-to-end architecture and cross-domain integration of compute and memory subsystems on IPU/DPU platforms.

• Define and evolve multi-level cache hierarchy (private/shared/system-level caches) and coherency models across cores, accelerators, and IO subsystems.
• Architect high-performance memory subsystems: DDR/LPDDR/HBM interfaces, memory controllers, scheduling policies, and bandwidth provisioning strategies.
• Design SMMU/IOMMU and IO-memory virtualization features for multi-tenant, virtualized workloads and secure isolation.
• Integrate compute, network (packet processing), storage, and accelerator subsystems to optimize data movement and minimize latency and copies.
• Define power, DVFS, and per-subsystem scaling strategies to optimize performance-per-watt and system efficiency.
• Lead multi-generation architecture roadmaps: core scaling, memory bandwidth/capacity, cache topology, and migration strategies across product lines.
• Collaborate cross-functionally with NSS, SoC fabric/interconnect, firmware/OS/drivers, and validation/performance teams to align architecture and resolve tradeoffs.

Requirements

Must-have technical experience and skills.

• Minimum 10+ years of experience in SoC/CPU/memory subsystem architecture and system-level architecture.
• Deep expertise in CPU architecture and cache hierarchies, including coherency domains and tradeoffs between latency, bandwidth, and scalability.
• Experience with memory subsystems (DDR/HBM), memory controllers, QoS, and bandwidth/scheduling strategies.
• Knowledge of coherent and non-coherent interconnect architectures and system-level PPA (performance, power, area) tradeoff analysis.
• Proven track record of driving architecture definition from concept through to silicon delivery.

Nice-to-have (preferred) skills.

• Experience with ARM and x86 compute and memory subsystem architectures, including NUMA and large-scale platform designs.
• Experience with IPU/SmartNIC or accelerator-centric SoCs targeting cloud and hyperscale environments.
• Familiarity with PCIe, CXL, and memory semantics for high-performance IO.
• Proven multi-generation architectural ownership and mentoring of other architects.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or another STEM-related field is required. Preferred: Post-graduate degree in Electrical Engineering, Computer Engineering, or related STEM field. (The posting specifies degree requirements explicitly.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.