SoC Compute/Memory Subsystem Architect

Job Title

SoC Compute/Memory Subsystem Architect

Role Summary

The role owns end-to-end architecture of compute complexes, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms. The position sits in a networking architecture team focused on high-performance, hyperscale data center platforms.

Experience Level

Senior — requires 10+ years of relevant industry experience in SoC, CPU, or memory subsystem architecture.

Responsibilities

Design and drive system-level compute and memory architecture to meet performance, scalability, power, and programmability goals.

• Define and evolve multi-level cache hierarchies and coherency models across cores, accelerators, and IO subsystems.
• Architect system memory subsystems: DDR/LPDDR/HBM interfaces, memory controllers, QoS and scheduling, and bandwidth scaling strategies.
• Design SMMU/IOMMU and IO memory virtualization for multi-tenant, secure IPU/DPU workloads.
• Integrate compute, network, storage, and accelerators to optimize data movement and minimize latency and copies.
• Define power, DVFS, and scaling strategies including bandwidth throttling and per-subsystem scaling.
• Lead multi-generation architecture roadmap and ensure migration/backward compatibility across product lines.
• Collaborate cross-functionally with networking, fabric/interconnect, firmware, OS/drivers, validation, and performance teams to align architecture and resolve tradeoffs.

Requirements

Must-have technical experience and skills; preferred items listed separately.

• 10+ years of hands-on experience in SoC/CPU/memory subsystem architecture and driving architecture from concept to silicon.
• Deep knowledge of CPU architecture and cache hierarchies, including coherent/non-coherent interconnect models.
• Experience with memory subsystems (DDR, HBM), memory controllers, bandwidth provisioning, and QoS.
• System-level performance analysis and PPA tradeoff experience (latency, bandwidth, scalability, power).
• Experience specifying interfaces and interactions between compute, network, storage, and accelerators.
• Strong cross-functional leadership, systems thinking, and decision-making under ambiguity.

Nice-to-have:

• Experience with IPU/SmartNIC, accelerator-centric SoCs, or hyperscale/cloud platforms.
• Familiarity with PCIe, CXL, and advanced memory semantics for high-performance IO.
• Track record of multi-generation architectural ownership and mentoring other architects.
• ARM and x86 compute and memory subsystem experience, including NUMA and large-scale platform architectures.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or another STEM field is required. Preferred: a postgraduate degree (Master's or PhD) in Electrical Engineering, Computer Engineering, or a related STEM field.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.