SoC Architect — Low Power Design (HBM)

Job Title

SoC Architect — Low Power Design (HBM)

Role Summary

As a Low Power Architect within the Heterogeneous Integration Group (HIG), you will define, model, and drive SoC-level power architecture for next-generation HBM logic die and memory-centric SoCs. The role requires cross-functional collaboration with architecture, RTL, verification, physical design, firmware, and product teams to deliver performance-per-watt solutions under power, thermal, and reliability constraints.

Experience Level

Senior — typically 10+ years of relevant industry experience with demonstrated architectural ownership and mentorship.

Responsibilities

Accountable for SoC power architecture, modeling, implementation, validation, and technical leadership across teams.

• Define and own SoC-level low-power architecture: power domains, voltage islands, clocking strategies, and low-power modes (active, idle, retention, sleep).
• Develop power, performance, and thermal models to evaluate architectural tradeoffs and guide PPA optimization across workloads.
• Architect and drive implementation of DVFS, clock gating, power gating, retention strategies, and adaptive performance controls.
• Translate product requirements into power-aware micro-architectural specifications with subsystem architects.
• Partner with RTL, verification, and physical design teams to ensure correct power intent implementation (e.g., UPF/CPF) and debug power-related functional and timing issues.
• Work with firmware and software teams to define hardware-software power management interfaces, sequencing, and control flows.
• Perform performance vs. power analysis to support product decisions, roadmap planning, and customer requirements.
• Support pre-silicon validation and post-silicon bring-up, including silicon power characterization, model correlation, and root-cause analysis.
• Contribute to architectural documentation and design reviews and lead cross-functional technical discussions.
• Mentor junior architects and engineers and promote best practices in low-power design.

Requirements

Must-have skills and experience.

• Proven SoC or system-level architecture experience focused on low-power or energy-efficient design.
• Deep knowledge of power management techniques: DVFS, power gating, clock gating, voltage regulation, and low-power state machines.
• Experience with power modeling, analysis, and trade-off studies at system and block level.
• Familiarity with hardware/software interactions that impact power efficiency.
• Working knowledge of RTL design concepts and low-power implementation flows (SystemVerilog, UPF/CPF).
• Experience across the RTL-to-GDS flow, including synthesis, STA, and power sign-off considerations.
• Programming or scripting experience (Python, C/C++, TCL) and strong cross-functional communication and leadership skills.
• Ability to work effectively in a global engineering environment.

Education Requirements

Preferred: Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical field. The posting does not specify a minimum required degree.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.