SMTS-Verification IP
SiemensRole Summary
The SMTS-Verification IP role at Siemens involves developing comprehensive verification IPs for various interfaces like PCIe Gen5/Gen6, USB3.2, and more. The position entails collaboration with design teams to enhance verification components and resolve customer issues.
Experience Level
Mid-level, preferably with 3-5 years of experience in verification engineering.
Responsibilities
The main responsibilities include:
- Specifying, implementing, testing, and enhancing verification components.
- Utilizing technologies covering SV, UVM, Assertions, and Coverage.
- Collaborating with Technical Marketing Engineers and Field Application Engineers.
Requirements
The ideal candidate should meet the following requirements:
- B.Tech/M.Tech in Electronics Engineering or related fields from reputed institutes.
- Strong expertise in verification engineering with hands-on experience.
- Proficient in System Verilog and familiar with verification methodologies like UVM.
- Intimate knowledge of protocols such as PCIe, USB, and others.
Education Requirements
B.Tech or M.Tech in Electronics Engineering or related fields.
About the Company
Company: Siemens
Headquarters: Munich, Germany
Siemens EDA is a leading global provider of Electronic Design Automation (EDA) products and systems. Their innovative solutions enable companies to enhance the development of electronic products efficiently and effectively, keeping pace with the complex demands of technology and physics. Siemens is committed to delivering advanced workflow solutions that integrate both EDA and MCAD tools for multi-domain design and manufacturing in the semiconductor industry.
