SMTS Design Engineer, Bonding and Packaging

Job Title

SMTS Design Engineer, Bonding and Packaging

Role Summary

Lead the electrical, thermal, and thermo-mechanical design and characterization of next-generation semiconductor packages (HBM, wafer-to-wafer, chip-on-wafer, flip chip, TSV). Work with global R&D, suppliers, vendors, and manufacturing to convert multiphysics simulation and test data into practical design rules and technology roadmaps. Drive integration of AI/ML tools to accelerate simulation, analysis, and data-driven decision making.

Experience Level

Senior-level. The posting requests 15–25 years of professional engineering experience with at least 10 years of direct experience in electrical, thermal, and mechanical package analysis, modeling, and validation.

Responsibilities

Primary responsibilities include advancing package designs through analysis, simulation, testing, and collaboration with internal and external partners.

• Maintain subject-matter expertise in advanced packaging technologies (HBM, wafer-to-wafer, chip-on-wafer, flip chip, TSV).
• Perform multiphysics simulations to quantify electrical parasitics, insertion loss, and impedance behavior across materials, geometries, temperature, and humidity.
• Propose and lead thermal improvement projects and contribute to thermal roadmaps; quantify layer contributions to overall thermal impedance.
• Analyze chip-package interactions for 2.5D and 3D systems; run sensitivity studies and validate mechanical and thermo-mechanical structural models.
• Define and coordinate test plans with vendors and labs to characterize material dielectric properties and other simulation inputs.
• Integrate AI/ML and generative AI into package design workflows, simulation acceleration, and technology evaluations.
• Translate simulation results into clear design rules and actionable recommendations for partnering teams.

Requirements

Key qualifications, split into must-have and preferred items.

• Must-have: 15–25 years of professional experience in a relevant engineering area with at least 10 years of direct experience in electrical, thermal, and mechanical package analysis, modeling, and validation in the semiconductor industry or equivalent.
• Must-have: Deep practical understanding of thermal performance drivers and ability to quantify thermal impedance contributions by layer.
• Must-have: Proficiency with Design of Experiments and statistical analysis tools (e.g., JMP or equivalent).
• Must-have: Demonstrated experience applying AI/ML and generative AI tools to engineering workflows and technical assessments.
• Must-have: Proven experience with multiphysics simulation and correlating models to measurement for electrical, thermal, and mechanical behavior of packages.
• Nice-to-have: Signal integrity analysis and high-speed package design experience; defining characterization plans and DOEs.
• Nice-to-have: Familiarity with Cadence layout tools for reviewing test vehicles and memory concepts.
• Nice-to-have: Data acquisition and numerical analysis skills (MATLAB, Excel, JMP, etc.).

Education Requirements

MS or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, or a related technical field as specified in the posting.

Micron is an equal opportunity employer.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.