Silicon Domain Architect

Job Title

Silicon Domain Architect

Role Summary

Join Intel's AI Silicon Architecture and Performance Engineering team to develop and maintain SystemC/TLM-based performance models that guide architecture exploration and product decisions for AI SoC platforms. The role focuses on modeling and analysis of communication fabrics, memory subsystems, scale-up/scale-out interconnects, and end-to-end data movement.

The position requires cross-functional technical leadership, close collaboration with architects and silicon teams, and delivery of data-driven recommendations that influence product architecture and scalability.

Experience Level

Senior - requires extensive experience; the posting specifies 15+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, performance engineering, or related domains.

Responsibilities

Key responsibilities include modeling, validation, analysis, data workflows, and cross-functional leadership:

• Develop, maintain, and improve SystemC/TLM performance models for SoC fabrics, memory subsystems, and data movement paths.
• Implement architectural features in models and improve model fidelity, scalability, and simulation performance.
• Define and execute validation strategies, regression suites, and correlation against simulations and hardware measurements.
• Design and run performance studies across workloads and configurations to identify bottlenecks and scalability limits.
• Analyze bandwidth, latency, congestion, buffering, and resource utilization across local, host, and remote memory domains.
• Create automated data collection, processing, analytics pipelines, and visualization dashboards for performance KPIs.
• Engage with architects, design teams, and stakeholders to review proposals and present performance-driven recommendations.
• Drive methodology improvements, automation, mentoring, and knowledge sharing to raise team capabilities.

Requirements

Must-have technical skills, experience, and behaviors:

• 15+ years of industry experience in performance modeling, architecture, or performance engineering.
• Strong C++ software development skills and working proficiency in Python for automation and data analysis.
• Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
• Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or complex hardware systems.
• Deep technical knowledge of SoC architecture, memory subsystem design, memory controllers, cache hierarchies, and data movement architectures.
• Experience with on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.
• Strong debugging, root-cause analysis, and quantitative reasoning skills; experience creating validation strategies and performance evaluation methodologies.
• Proven communication and stakeholder management skills; ability to present technical findings to engineering leadership and influence decisions.
• Nice-to-have: familiarity with AI/ML workloads, distributed training/inference, performance stimulus generation, and dashboarding tools (Power BI, Tableau, Grafana, Plotly, etc.).

Education Requirements

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.