Silicon Design Validation, Senior Manager

Job Title

Silicon Design Validation, Senior Manager

Role Summary

The Senior Manager, Silicon Design Validation leads a team responsible for post-silicon validation, characterization, and production release of advanced FPGA and IP products. The role provides technical direction and strategic oversight across silicon bring-up, test enablement, and datasheet characterization.

This position is focused on ensuring product quality and performance through validation planning, infrastructure, RTL test logic, and cross-functional coordination with design, manufacturing, test, and applications teams.

Experience Level

Senior — 15+ years of experience in silicon validation, including approximately 3–5 years in a leadership or management role.

Responsibilities

The role combines technical leadership, team development, and hands-on coordination of post-silicon activities. Key responsibilities include:

• Lead post-silicon lifecycle activities from first-silicon bring-up through production qualification and release.
• Define and execute validation and characterization strategies for analog, digital, and mixed-signal IPs.
• Oversee development of validation plans, bench hardware and software requirements, and necessary lab infrastructure and tools.
• Supervise creation of RTL test logic and FPGA-based test implementations to enable targeted validation and characterization.
• Drive silicon bring-up, debug, datasheet parameter characterization, and statistical analysis of measured data.
• Coordinate cross-functional work with design, verification, manufacturing, test, quality, and product teams to ensure timely product delivery.
• Provide leadership for post-release customer issue resolution and escalations.
• Foster a learning culture and technical skill development within the validation team.

Requirements

Must-have technical skills and experience for immediate success in this role:

• 15+ years of hands-on experience in silicon validation with proven delivery on complex validation projects.
• 3–5 years of people management or technical leadership experience.
• Deep expertise in high-speed SerDes interface characterization and protocol compliance testing (examples: PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, CSI/DSI-2, USB, DisplayPort, HDMI).
• Strong background in high-speed board design, signal integrity evaluation, and debug methodologies.
• Proficiency in Verilog/VHDL and FPGA design implementation using industry-standard flows.
• Experience developing test automation and bench-control software (Python, Perl).
• Practical knowledge of statistical analysis tools and methods (for example JMP, R) for datasheet characterization.
• Hands-on experience with lab equipment such as BERTs, VNAs, high-speed oscilloscopes, and protocol analyzers.
• Exposure to FPGA-based emulation and hardware prototyping platforms.
• Strong written and verbal communication skills, critical thinking, and problem-solving orientation.

Nice-to-have:

• Experience characterizing DDR memory interfaces (DDR4, LPDDR4, DDR5), PLLs, DSP blocks, MIPI, and I/O subsystems.
• Prior work in product datasheet preparation and statistical reporting for silicon products.

Education Requirements

Master's or Bachelor's degree in Electrical Engineering.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.