Silicon Architect, Subsystem Architecture

Job Title

Silicon Architect, Subsystem Architecture

Role Summary

Work on on-chip memory architecture for accelerator subsystems in wearable SoCs, balancing power, performance and area (PPA) under tight budgets. The role sits on the Reality Labs Silicon Subsystem Architecture team and collaborates with memory, IP, circuit, DSP, firmware and software teams across programs.

Experience Level

Entry-level (2+ years of relevant silicon architecture or memory-design experience).

Responsibilities

Perform analysis and trade studies to define memory for accelerator subsystems and inform architecture decisions.

• Analyze memory requirements per workload across accelerator subsystems (caches, scratchpads, DSP local memories).
• Evaluate SRAM options (compiled/custom, bitcell choices, banking, low-voltage and retention modes) and recommend best fit.
• Build memory models and PPA comparisons to guide architectural trade-offs.
• Study memory hierarchy trade-offs (cache sizing, on-chip vs off-chip) and own end-to-end analysis for one or more subsystems.
• Track and assess emerging memory technologies (MRAM, RRAM, eDRAM, 3D-stacked, compute-in-memory) for subsystem use.
• Correlate estimates with pre-silicon and silicon data and improve modeling methodologies.
• Collaborate with senior memory architects, IP/DSP architects, circuit designers, and software/firmware teams.

Requirements

Must-have technical skills and experience required to perform the role; listed separately are useful but not required items.

• Must-have: Minimum 2 years of experience in silicon architecture, memory design, or related silicon engineering disciplines.
• Must-have: Experience (industry, internships or graduate research) in at least one of: memory hierarchy and cache analysis, or SRAM circuit design.
• Must-have: Understanding of how memory technologies and microarchitectures (e.g. SRAM bitcell, Vmin, leakage, banking) affect power, performance and area of memory-intensive systems.
• Must-have: Experience building analytical, functional and cycle-accurate models to evaluate memory trade-offs.
• Nice-to-have: Publications in ISCA/MICRO/HPCA/ISSCC/VLSI symposium.
• Nice-to-have: Experience with SPICE, memory compilers, low-voltage SRAM, or SRAM circuit tuning.
• Nice-to-have: Experience sizing caches, scratchpads or DSP memories for accelerator workloads and research or industry experience with emerging memory technologies.
• Nice-to-have: Experience spanning both memory hierarchy/cache analysis and SRAM circuit design.

Education Requirements

Requires a Bachelor's degree in Computer Science, Computer Engineering or a relevant technical field, or equivalent practical experience. Candidates may be in the process of completing a Bachelor's but the degree must be completed prior to joining Meta. Preferred: PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with research in memory systems or memory circuits.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.