Silicon Architect, AI Accelerator
MatXJob Title
Silicon Architect, AI Accelerator
Role Summary
Define and deliver compute architecture for next-generation GenAI accelerators at the full-chip or subsystem level. Focus areas include ISA, connectivity, memories, control, and tradeoffs among power, performance, and area.
Work cross-functionally with research, software, and hardware teams to convert AI workloads into performant, programmable silicon and support first-silicon bring-up and post-silicon debug.
Experience Level
Senior-level. The posting does not state explicit years of experience; the role expects experienced architects for system- or chip-level design.
Responsibilities
Primary responsibilities include defining compute architecture, performing analysis, and collaborating across teams.
- Define AI compute subsystem architecture: ISA, interconnects, memories, and control mechanisms.
- Derive architectural requirements from AI workloads and use cases.
- Perform analytical and empirical performance analysis to guide design decisions.
- Collaborate with research, software, and hardware teams to ensure workload fit, programmability, and PPA targets.
- Evaluate power/area/performance trade-offs with stakeholders.
- Support test plan reviews, first-silicon bring-up, and post-silicon debug and validation.
Requirements
Must-have technical capabilities and skills; one concise list for required and optional items.
- Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures.
- Experience mapping workloads to hardware architecture and deriving architecture-level requirements.
- Solid microarchitecture fundamentals and first-principles understanding of latency, throughput, utilization, and scalability.
- Familiarity with numeric formats, quantization, rounding, and precision/performance trade-offs.
- Programming, code optimization, or kernel-level performance analysis experience.
- Excellent written and verbal communication skills for cross-team collaboration and documentation.
- Nice-to-have: familiarity with performance-optimization techniques for large-scale transformer models.
Education Requirements
Not specified.
About the Company
Company: MatX
Headquarters: Mountain View, California, USA
MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.
