Signal & Power Integrity Hardware ASIC Simulation Engineer Lead

Job Title

Signal & Power Integrity Hardware ASIC Simulation Engineer Lead

Role Summary

Lead technical efforts to define, design, and verify signal and power integrity for advanced ASIC packaging and substrates used in high-performance networking products. Work with ASIC architects, package/layout teams, vendors, and system partners to deliver production-ready ASIC/package solutions.

Experience Level

Senior - technical lead role with multi-year experience required (see Education Requirements for exact experience-by-degree guidance).

Responsibilities

Deliver SI/PI analysis, define design rules, and guide cross-functional teams through ASIC/package development.

• Develop, document, and implement ultra-high-speed signaling and PI design rules to meet power, performance, and area targets.
• Perform SI/PI analysis of interposer, substrate, and PCB; provide actionable feedback to layout and package teams.
• Lead post-layout extraction, reporting, and physical design validation to support high-volume product release.
• Collaborate with vendors and system partners to resolve complex SI/PI issues and define combined power/signal integrity solutions.
• Participate in chip-architecture discussions and review IC and analog/mixed-signal circuit designs for SI/PI implications.
• Mentor junior SI/PI engineers and promote design reviews, postmortems, and continuous improvement practices.

Requirements

Must-have technical skills and tools experience for immediate contribution.

• Expertise in high-speed design principles: transmission line theory, electromagnetics, S-parameters, impedance networks, channel modeling, and BER prediction for high-rate SerDes (e.g., 56G PAM4).
• Proven SI/PI simulation experience with industry tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Experience with layout review and physical validation flows (examples: Cadence APD, Ansys EM) to validate signal performance and mitigate crosstalk.
• Practical circuit-level analysis using SPICE or equivalent for signal modeling and performance validation.
• Ability to define processes, methods, and tools for complex ASIC/package developments and to drive cross-functional technical decisions.

Nice-to-have:

• Experience with HBM or other high-speed memory interfaces and die-to-die interfaces (UCIe or proprietary).
• Experience with advanced packaging technologies (CoWoS, EMIB, interposer-based 2.5D designs) and SI/PI of such systems.
• Familiarity with Vector Network Analysis and IBIS modeling.
• Strong verbal and written communication skills for technical audiences.

Education Requirements

Degree-based experience requirement: Bachelor's in Electrical Engineering with 8+ years of relevant SI/PI experience; or Master's in Electrical Engineering with 6+ years; or PhD in Electrical Engineering with 3+ years. (Requirement is degree plus specified years as stated.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).