Signal and Power Integrity Lead Application Engineer

Job Title

Signal and Power Integrity Lead Application Engineer

Role Summary

Customer-facing technical lead in Cadence's Application Engineering organization based at one of the France offices (Vélizy, Sophia, or Grenoble). The role provides SI/PI expertise for IC package and PCB designs, using simulation and EM extraction tools to help customers validate high-speed interconnects and power distribution networks.

Work involves direct customer engagement, technical presentations, training, and collaboration with sales and R&D to deliver practical solutions that enable customer sign-off on designs.

Experience Level

Senior level. The posting requests 3–6 years of relevant Signal Integrity / Power Integrity or electromagnetic design experience; title indicates a lead/senior role and requires demonstrated customer-facing technical expertise.

Responsibilities

Primary customer-facing and technical responsibilities include:

• Perform SI and PI analysis in time and frequency domains to support design validation and sign-off.
• Apply SI/PI methodologies (IBIS, TDR, impedance control, transmission line theory, PDN characterization) across IC packages and PCBs.
• Conduct IR-drop and AC PDN optimization to meet impedance and power-ripple targets.
• Design and configure system-level, time-domain test benches using IBIS-AMI and interconnect structures for high-speed protocol sign-off (e.g., DDR5, LPDDR5, PCIe 5).
• Use 2.5D/3D EM extraction and solver workflows to analyze interconnects and support validation.
• Lead technical evaluations and campaigns with customers; deliver clear technical presentations to varied audiences.
• Train and onboard customers on SI/PI workflows and EM extraction tools; build trusted customer relationships with on-site visits (approx. 20–30% travel within France).
• Collaborate with internal sales, product engineering, and R&D teams and contribute to the global Application Engineering community.

Requirements

Must-have skills and conditions:

• 3–6 years of practical experience in Signal Integrity, Power Integrity, or related electromagnetic design roles.
• Strong background with EDA tools and IC package and PCB design methodologies.
• Proficiency in SI/PI simulation workflows, including PDN analysis, high-speed protocol characterization, and EM model extraction.
• Experience with high-speed interfaces such as DDR5/LPDDR5 and PCIe 5.
• Fluency in French and English (both written and spoken) for direct customer engagement and internal collaboration.
• Valid work and residence permit for employment in France.

Nice-to-have:

• Hands-on experience with Cadence Sigrity tools and/or the Clarity 3D EM solver.
• Familiarity with thermal analysis alongside SI/PI workflows.
• Experience presenting technical content to both technical and non-technical audiences in customer-facing or pre-sales roles.
• Exposure to emerging interconnect standards such as UCIe or CEI-OIF.

Education Requirements

Master's degree in Electrical Engineering, Electronics Engineering or a closely related technical field, or equivalent professional experience.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.